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標題: [硬件] Ivy Bridge Info Thread(Updated#2 30-11-2011, @#122) [打印本頁]
作者: ccw    時間: 2011-7-2 22:08     標題: Ivy Bridge Info Thread(Updated#2 30-11-2011, @#122)

Ivy's first bench, [email protected], in TW.

http://www.chiphell.com/forum-vi ... rby%3Ddateline.html

Ivy's second bench, [email protected], in China

http://news.mydrivers.com/1/198/198292.htm

三代i3比拼：22nm Ivy Bridge详细评测

http://news.mydrivers.com/1/198/198969.htm

Intel Ivy Bridge Corescn 首测
自从上个月12日Corescn第一次爆光Ivy Bridge以来将近一个月了！今天终于有机会完成部分测试给大家参考一下Ivy 的实际性能。因为目前拿到的Ivy 基本都为早期版本或多或少都存在一些Bug。就像前段时间各大媒体测试AMD Bulldozer 成绩也不是很理想，所以Corescn 给大家带来的测试就当做了解新品！
1.       首先给大家来介绍一下今天要测试的Ivy Bridge 基本信息，Corescn 拿到的2颗Ivy ES版CPU 分别为 QAX2 ,QAX3
QAX2 主频1.8G,4核8线程，L3最大8M，最大倍频18最小倍频13，外频同SNB相同为100MHz ，内存Controller Frequency 达到1600. 不支援Turbo Boost

QAX3 主频1.8G,2核4线程，L3最大4M，最大倍频18最小倍频13，外频同SNB相同为100MHz ，内存Controller Frequency 达到1600. 不支援Turbo Boost

[attach]16239[/attach]

按照惯例也顺便找了一颗SNB I5 做对比测试。因资源有限，就随意选择的I5 2320 做参考。
CPU 信息参考如下

[attach]16240[/attach]

2 测试部分
文件压缩测试——7-Zip 9.23
7-Zip压缩测试 数值越大越好

[attach]16241[/attach]

7-Zip解压缩测试 数值越大越好

[attach]16242[/attach]

2 .专业渲染测试——CINEBENCH R11.5
数值越大越好

[attach]16243[/attach]

3.算术性能测试——Super Pi
数值越小越好

[attach]16244[/attach]

4.异构计算测试—HC Benchmark
数值越大越好

[attach]16245[/attach]

总结：从测试成绩来看主频只有1.8G的Ivy表现还是不错的。没记错的话目前网络上Bulldozer 8core 样品Super Pi成绩和解压成绩都要逊色。虽然和现在主流产品SNB测试成绩有差距,但是我们可看看i5 2320拥有3G的主频.在以上测试软件上对于主频的要求还是比较高的！所以相信在后续高主频版的Ivy定会有不错的成绩！

http://www.corescn.com/thread-931-1-1.html

Ivy Bridge确定明年四月发布 赛扬要没了

Intel 22nm Ivy Bridge原计划在2012年年初发布，但因为PC市场需求疲软的缘故(也有说是生产工艺问题)推迟到3-4月份，且早已被官方路线图证实。现在，更确切的发布规划来了。

据了解，Ivy Bridge将于2012年4月的某一天开始发布，但不像Sandy Bridge那样整个家族集体登场，首批只会有桌面版的Core i7/i5和移动版的Core i7，也就是仅仅是中高端部分。当然，配套的7系列芯片组和主板也会开始同步登场，但不知道会不会一次性出齐。

等到第二季度晚些时候，第二波来临，包括桌面和移动版的Core i5/i3系列，面向主流市场。

然后再到第三季度就是新一代桌面Pentium，奔腾这个经典老品牌也将继续征战入门级市场。

这么看来第四季度就是Celeron赛扬了，那你就错了，至少按照现在的规划，Ivy Bridge家族不会出现新的赛扬型号，无论桌面上还是笔记本上都不会，均将停留在Sandy Bridge时代。当然了，也不排除随着形势的变化Intel又改主意的可能性，但从目前看来，赛扬可能真的要休息了。

http://news.mydrivers.com/1/210/210239.htm

[ 本帖最後由 ccw 於 2011-11-30 15:14 編輯 ]
作者: qcmadness    時間: 2011-7-5 19:08

預計會同SB freq差唔多
作者: qcmadness    時間: 2011-7-6 01:04

引用:
原帖由 ccw 於 2011-7-5 20:10 發表

It looks around 15-20% improvement for the same frequency from SB.
INT or FP or SIMD or AVX?
作者: ccw    時間: 2011-7-6 01:21

引用:
原帖由 qcmadness 於 2011-7-6 01:04 發表

INT or FP or SIMD or AVX?
I am not sure, just a rumor from the web and a guess based on the bench.
作者: qcmadness    時間: 2011-7-6 01:26

引用:
原帖由 ccw 於 2011-7-6 01:21 發表

I am not sure, just a rumor from the web and a guess based on the bench.
等出左先算...
作者: ccw    時間: 2011-7-6 01:32

引用:
原帖由 qcmadness 於 2011-7-6 01:26 發表

等出左先算...
Somewhat I want to predict how much I will lose for buying a Sandy in Sep, and if it is worthwhile to further suspend the plan, through quite impossible.
作者: qcmadness    時間: 2011-7-6 01:40

引用:
原帖由 ccw 於 2011-7-6 01:32 發表

Somewhat I want to predict how much I will lose for buying a Sandy in Sep, and if it is worthwhile to further suspend the plan, through quite impossible.
it depends on usage

if you need multi-thread performance, SB-E, BD, will be better than IVB
作者: ccw    時間: 2011-7-6 01:47

引用:
原帖由 qcmadness 於 2011-7-6 01:40 發表

it depends on usage

if you need multi-thread performance, SB-E, BD, will be better than IVB
Yes, but another question is I want to utilize ECC memory at the same time, I am not sure if SB-EP is still that avoidable to me.
And I am not sure about building an Opteron system, I cannot see a single CPU mainboard with G34 socket.
作者: qcmadness    時間: 2011-7-6 01:55

引用:
原帖由 ccw 於 2011-7-6 01:47 發表


Yes, but another question is I want to utilize ECC memory at the same time, I am not sure if SB-EP is still that avoidable to me.
And I am not sure about building an Opteron system, I cannot see a s ...
Socket G34 is for 2-4 socket systems
作者: ccw    時間: 2011-7-6 09:08

引用:
原帖由 qcmadness 於 2011-7-6 01:55 發表

Socket G34 is for 2-4 socket systems
It looks the upcoming bulldozer Opteron uses only Socket G34,
so it maybe hard to take BD as a choice.
作者: qcmadness    時間: 2011-7-6 09:19

引用:
原帖由 ccw 於 2011-7-6 09:08 發表

It looks the upcoming bulldozer Opteron uses only Socket G34,
so it maybe hard to take BD as a choice.
C32 also, but nearly the same infrastructure with Socket AM3+
And C32 is optimized for performance/power but not max performance
作者: ccw    時間: 2011-7-6 10:24

引用:
原帖由 qcmadness 於 2011-7-6 09:19 發表


C32 also, but nearly the same infrastructure with Socket AM3+
And C32 is optimized for performance/power but not max performance
Thanks for telling, I may take a look on the feasibility on building with those parts later.
作者: qcmadness    時間: 2011-7-6 10:26

引用:
原帖由 ccw 於 2011-7-6 10:24 發表

Thanks for telling, I may take a look on the feasibility on building with those parts later.
If you want a workstation, SB-E is your only choice
作者: ccw    時間: 2011-7-6 10:38

引用:
原帖由 qcmadness 於 2011-7-6 10:26 發表

If you want a workstation, SB-E is your only choice
Not really a workstation, but a stable machine with satisfactory performance lasting for around 4 years within budget.
Therefore Xeon E3 should be a right choice for me, I simply thinking that if there can be more options.
作者: qcmadness    時間: 2011-7-6 10:42

引用:
原帖由 ccw 於 2011-7-6 10:38 發表

Not really a workstation, but a stable machine with satisfactory performance lasting for around 4 years within budget.
Therefore Xeon E3 should be a right choice for me, I simply thinking that if the ...
then you don't need ecc
作者: ccw    時間: 2011-7-6 10:58

引用:
原帖由 qcmadness 於 2011-7-6 10:42 發表

then you don't need ecc
You are correct with this,
I don't really need ECC but in case it is within budget, it is preferred.
I can accept the performance of SB Xeon and think that it would serve me well in a few years, so you may say that I can choose between
Xeon E3 + ECC or SB-E/BD w/o ECC.
If the SB-E workstation platform is much more expensive, I will go for SB Xeon......while I need more performance information to make that decision.
作者: qcmadness    時間: 2011-7-6 11:04

引用:
原帖由 ccw 於 2011-7-6 10:58 發表

You are correct with this,
I don't really need ECC but in case it is within budget, it is preferred.
I can accept the performance of SB Xeon and think that it would serve me well in a few years, so y ...
SB-E will be of ~3GHz range with 6c12t
作者: ccw    時間: 2011-7-6 11:16

引用:
原帖由 qcmadness 於 2011-7-6 11:04 發表

SB-E will be of ~3GHz range with 6c12t
That would no doubt be bringing a performance boost with 2C4T more, and also the quad channel memory will favor the editing in Photoshop, that is quite critical to me.
But the point is still on the budget, and for more performance, I prefer an stability enhancement with ECC memory. Still hard to make the decision without price and performance data of SB-E and BD......
作者: qcmadness    時間: 2011-7-6 11:18

引用:
原帖由 ccw 於 2011-7-6 11:16 發表

That would no doubt be bringing a performance boost with 2C4T more, and also the quad channel memory will favor the editing in Photoshop, that is quite critical to me.
But the point is still on the b ...
ECC is useless for your intended usage...
作者: ccw    時間: 2011-7-6 11:26

引用:
原帖由 qcmadness 於 2011-7-6 11:18 發表

ECC is useless for your intended usage...
Yes, so I always say that it is possible I get a BD/SB-E instead of Xeon E3, and here I prefer Xeon over i7 just because I don't need to OC and ECC memory is not putting an extra to system cost.

While actually time is also critical for me, I don't want to spend too much time waiting.
Probably I will choose between BD and SB in Sep,
Now SB-E is delayed to next year, very unlikely I will wait for it unless before I have taken action there is an extraordinary bench from SB-E.
作者: ccw    時間: 2011-7-12 21:30

updated, see #4
作者: ccw    時間: 2011-8-19 15:49

Updated
作者: ccw    時間: 2011-9-12 23:26     標題: Ivy Bridge Configurable TDP Detailed

http://www.anandtech.com/show/47 ... urable-tdp-detailed
作者: ccw    時間: 2011-9-12 23:27     標題: Ivy Bridge GPU Performance: Up to 60% Faster than SNB & Better QuickSync

http://www.anandtech.com/show/47 ... nb-better-quicksync
作者: qcmadness    時間: 2011-9-12 23:28

我諗主要係support DX11多過真係效能上升...
實際效能在無乜其他特別增強, 好難真係快60%

不過+60%同Trinity claim既+50%, 其實又差唔多
即係距離其實無縮少到
作者: ccw    時間: 2011-9-15 09:40     標題: Ivy Bridge：14亿个晶体管 支持DDR3-2800

http://news.mydrivers.com/1/204/ ... om/1/204/204271.htm

2800
作者: qcmadness    時間: 2011-9-15 10:45

引用:
原帖由 ccw 於 2011-9-15 09:40 發表
http://news.mydrivers.com/1/204/ ... om/1/204/204271.htm

2800
2133以上無乜實際意義...
作者: qcmadness    時間: 2011-9-15 20:04

intel SB報流料
作者: cheungmanhoi    時間: 2011-9-15 20:05

引用:
原帖由 qcmadness 於 2011-9-15 20:04 發表
intel SB報流料
咩流料?
作者: qcmadness    時間: 2011-9-15 20:09

引用:
原帖由 cheungmanhoi 於 2011-9-15 20:05 發表

咩流料?
發佈果陣一路都話係995M transistor (4-core version)
而家有人追問IVB transistor count

一口氣將SB個transistor count推上1140M
咁佢同BD個competitive advantage無左一大半
作者: ccw    時間: 2011-9-15 20:35

引用:
原帖由 qcmadness 於 2011-9-15 20:09 發表

發佈果陣一路都話係995M transistor (4-core version)
而家有人追問IVB transistor count

一口氣將SB個transistor count推上1140M
咁佢同BD個competitive advantage無左一大半 ...
Maybe the advantage of Tri-Gate should be taken into account; the advancement may cover the loss due to the transistor number boost.
作者: qcmadness    時間: 2011-9-15 20:40

引用:
原帖由 ccw 於 2011-9-15 20:35 發表

Maybe the advantage of Tri-Gate should be taken into account; the advancement may cover the loss due to the transistor number boost.
咁做咩要出假SB transistor count
作者: ccw    時間: 2011-9-15 20:44

引用:
原帖由 qcmadness 於 2011-9-15 20:40 發表

咁做咩要出假SB transistor count
Sorry, looks I misunderstood your words, any more details?
作者: qcmadness    時間: 2011-9-15 20:45

引用:
原帖由 ccw 於 2011-9-15 20:44 發表

Sorry, looks I misunderstood your words, any more details?
SB transistor count: 995M > 1160M
作者: ccw    時間: 2011-9-15 20:47

引用:
原帖由 qcmadness 於 2011-9-15 20:45 發表

SB transistor count: 995M > 1160M
I see, just spotted this on Anandtech,
wait for Intels ans then.
作者: qcmadness    時間: 2011-9-15 20:48

引用:
原帖由 ccw 於 2011-9-15 20:47 發表

I see, just spotted this on Anandtech,
wait for Intels ans then.
http://www.anandtech.com/show/4798/ivy-bridge-148b-transistors
作者: qcmadness    時間: 2011-9-16 01:36

http://www.anandtech.com/show/48 ... 5m-are-both-correct

愈講愈衰
作者: cheungmanhoi    時間: 2011-9-16 11:48

引用:
原帖由 qcmadness 於 2011-9-16 01:36 發表
http://www.anandtech.com/show/48 ... 5m-are-both-correct

愈講愈衰
無理解錯佢係唔係講DESIGN就995 TAPE OUT就1.16B
作者: qcmadness    時間: 2011-9-16 11:49

引用:
原帖由 cheungmanhoi 於 2011-9-16 11:48 發表

無理解錯佢係唔係講DESIGN就995 TAPE OUT就1.16B
咁應該報1.16B
作者: qcmadness    時間: 2011-9-18 09:49

http://www.anandtech.com/show/48 ... hitecture-exposed/1
引用:
As I mentioned above, Ivy Bridge finally supports USB 3.0 natively.
4 USB 3.0 ports across all high-end chipsets.
Still 2 SATA-3 and 4 SATA-2 ports.
引用:
Quad-core Ivy Bridge CPUs will support up to 8MB of L3 cache, and the private L1/L2s haven't increased from their sizes in Sandy Bridge (32+32K/256K).

The memory controller also remains relatively unchanged, aside from some additional flexibility. Mobile IVB supports DDR3L in addition to DDR3, enabling 1.35V memory instead of the standard 1.5V DDR3. This is particularly useful in notebooks that have on-board DDR3 on the underside of the notebook; OEMs can use DDR3L and keep your lap a bit cooler.
A little bit disappointment...
引用:
Memory overclocking also gets a bump in Ivy Bridge. The max supported DDR3 frequency in SNB was 2133MHz, Ivy Bridge moves this up to 2800MHz. You can now also increase memory frequency in 200MHz increments.
Good for OCers, but really useful?
引用:
The System Agent operates on a separate voltage plane than the rest of the chip. On Ivy Bridge Intel now offers even lower System Agent voltage options for the lower voltage SKUs, which in turn helps power optimize those SKUs.
Good for mobile...
引用:
The cTDP up mode is obviously for docked notebooks. You can imagine an Ivy Bridge notebook with an optional dock that could enhance the cooling capabilities of the machine. When undocked the notebook's processor would operate at a max TDP of 17W, for example, but toss it in a dock with additional cooling and the TDP would jump up to 33W. It's up to the OEMs to decide how they want to take advantage of this feature. It could be something as simple as a mobile dock with more fans, or something as complex as a modular water cooling solution with a bigger radiator in the dock. I haven't seen any concepts of systems that take advantage of Ivy Bridge's cTDP up support, but that's the theory.

What about cTDP down? Take the same 17W Ivy Bridge CPU from above but now drop the TDP to 13W, which in turn limits clock speed and voltage. Why would you want to do this? From the OEM perspective, Intel's TDP choices may seem arbitrary. Downwards configurable TDP allows OEMs to get a lower power configuration without forcing Intel to create a new SKU. OEMs can do this today through undervolting/underclocking of their own, but the cTDP down spec will at least give OEMs a guarantee of performance/power.
This is normal and is easily implemented in previous generations of Intel and AMD CPUs...
引用:
The Ivy Bridge GPU adds support for OpenCL 1.1, DirectX 11 and OpenGL 3.1. This will finally bring Intel's GPU feature set on par with AMD's. Ivy also adds three display outputs (up from two in Sandy Bridge). Finally, Ivy Bridge improves anisotropic filtering quality. As Intel Fellow Tom Piazza put it, "we now draw circles instead of flower petals" referring to image output from the famous AF tester.
Eyefinity iGPU version?
Better AF algorithm is always welcomed.
引用:
Ivy Bridge will bring about higher clock speeds thanks to its 22nm process, however the gains will likely be minimal at best. Intel hasn't been too keen on pursuing clock speed for quite some time now. Clock for clock performance will go up by a small amount over Sandy Bridge (4 - 6%), combine that with slightly higher clock speeds and we may see CPU performance gains of around 10% at the same price point with Ivy Bridge. The bigger news will be around power consumption and graphics performance.
This is the most worrying part, Intel surely wants to reduce costs rather than higher performance.
引用:
Ivy Bridge will be Intel's flagship 22nm CPU for some time. The chip was originally due out at the end of this year but was likely subject to delays due to issues with the fab process and the chip itself. The move to 22nm is significant leap. Not only are these new transistors aggressively small but the introduction of Intel's tri-gate technology is a major departure from previous designs. Should the fab engineers at Intel do their job well, Ivy Bridge could deliver much better power characteristics than Sandy Bridge. As we've already seen, introducing a 35W quad-core part could enable Apple (and other OEMs) to ship a quad-core IVB in a 13-inch system.
That's what I posted...
作者: ccw    時間: 2011-11-24 22:45     標題: Ivy Bridge确定明年四月发布 赛扬要没了

http://news.mydrivers.com/1/210/210239.htm
作者: qcmadness    時間: 2011-11-24 23:36

引用:
原帖由 ccw 於 2011-11-24 22:45 發表
http://news.mydrivers.com/1/210/210239.htm
mainly due to hdd shortage
作者: jackli    時間: 2011-11-24 23:50

其實無咩分別, 只系玩左tri-gate 3D
作者: ccw    時間: 2011-11-24 23:54

引用:
原帖由 jackli 於 2011-11-24 23:50 發表
其實無咩分別, 只系玩左tri-gate 3D
The difference reflected on the boards tbh.
作者: qcmadness    時間: 2011-11-25 00:09

引用:
原帖由 jackli 於 2011-11-24 23:50 發表
其實無咩分別, 只系玩左tri-gate 3D
this is not a 3-d gate at all
作者: ccw    時間: 2011-11-26 16:56

引用:
原帖由 qcmadness 於 2011-11-25 00:09 發表

this is not a 3-d gate at all
3D is just a gimmick
作者: Henry    時間: 2011-11-26 17:57

引用:
原帖由 qcmadness 於 2011-9-18 09:49 發表
http://www.anandtech.com/show/48 ... hitecture-exposed/1



4 USB 3.0 ports across all high-end chipsets.
Still 2 SATA-3 and 4 SATA-2 ports.



A little bit disappoi ...
都話Intel無AMD壓住CPU部份就開始Hea架啦.
DDR3 2800應該係俾GPU用，等兩邊唔使爭頻寬，同GPU效能提升。
作者: qcmadness    時間: 2011-11-26 17:58

引用:
原帖由 Henry 於 2011-11-26 17:57 發表

都話Intel無AMD壓住CPU部份就開始Hea架啦.
DDR3 2800應該係俾GPU用，等兩邊唔使爭頻寬，同GPU效能提升。
...

你知唔知點解intel / gf / tsmc要追製程先
唔知就唔好話佢hea

intel不知幾想愈快出愈好
作者: Henry    時間: 2011-11-26 18:02

引用:
原帖由 qcmadness 於 2011-11-26 17:58 發表

...

你知唔知點解intel / gf / tsmc要追製程先
唔知就唔好話佢hea

intel不知幾想愈快出愈好
我係話個CPU架構。
製程同產能方面Intel的確係不遺餘力。
作者: qcmadness    時間: 2011-11-26 18:03

引用:
原帖由 Henry 於 2011-11-26 18:02 發表

我係話個CPU架構。
製程同產能方面Intel的確係不遺餘力。
架構... 好快intel要學amd / nvidia攪 heterogeneous multi-core
single-thread performance開始難升了

方向係咁, 但係點做到, 3間都有唔同的盤算
作者: Henry    時間: 2011-11-26 18:10

引用:
原帖由 qcmadness 於 2011-11-26 18:03 發表

架構... 好快intel要學amd / nvidia攪 heterogeneous multi-core
single-thread performance開始難升了

方向係咁, 但係點做到, 3間都有唔同的盤算
NV粒Kai-EI已經係(4+1)，不過個效能成本方面的確值得考慮。始終要額外面積，而且係分開運行。
作者: qcmadness    時間: 2011-11-26 18:12

引用:
原帖由 Henry 於 2011-11-26 18:10 發表

NV粒Kai-EI已經係(4+1)，不過個效能成本方面的確值得考慮。始終要額外面積，而且係分開運行。
太少power profile
作者: Henry    時間: 2011-11-26 19:01

引用:
原帖由 qcmadness 於 2011-11-26 18:12 發表

太少power profile
如果Intel IB可以idle或部分Core開果陣可以關某幾個Core已經係省電上再進一步,四核Idle可以同單核睇齊,只用雙核既情況可以關雙核.
作者: qcmadness    時間: 2011-11-26 19:08

引用:
原帖由 Henry 於 2011-11-26 19:01 發表

如果Intel IB可以idle或部分Core開果陣可以關某幾個Core已經係省電上再進一步,四核Idle可以同單核睇齊,只用雙核既情況可以關雙核.
intel (nehalem or westmere?) / amd (llano) 已經做到
作者: Henry    時間: 2011-11-26 19:10

引用:
原帖由 qcmadness 於 2011-11-26 19:08 發表

intel (nehalem or westmere?) / amd (llano) 已經做到
關Core喎,做到?
作者: qcmadness    時間: 2011-11-26 19:10

引用:
原帖由 Henry 於 2011-11-26 19:10 發表

關Core喎,做到?
早就做到

你估gating死架?
作者: Henry    時間: 2011-11-26 19:16

引用:
原帖由 qcmadness 於 2011-11-26 19:10 發表

早就做到

你估gating死架?

但個Task manager都係Show 4/8條Thread?
作者: qcmadness    時間: 2011-11-26 19:17

引用:
原帖由 Henry 於 2011-11-26 19:16 發表


但個Task manager都係Show 4/8條Thread?
基本上係斷電

intel / amd都係
作者: Henry    時間: 2011-11-26 19:19

引用:
原帖由 qcmadness 於 2011-11-26 19:17 發表

基本上係斷電

intel / amd都係
但2/4 Full Load果陣呢?果兩個都會斷電?
作者: qcmadness    時間: 2011-11-26 19:20

引用:
原帖由 Henry 於 2011-11-26 19:19 發表

但2/4 Full Load果陣呢?果兩個都會斷電?
多數唔會
但主要係intel / amd power profile而唔係設計上唔得
作者: Henry    時間: 2011-11-26 19:23

引用:
原帖由 qcmadness 於 2011-11-26 19:20 發表

多數唔會
但主要係intel / amd power profile而唔係設計上唔得
Intel/AMD個Power Profile可能要再做野.
作者: qcmadness    時間: 2011-11-26 19:33

引用:
原帖由 Henry 於 2011-11-26 19:23 發表

Intel/AMD個Power Profile可能要再做野.
Android同Windows唔同, 係要做野.
作者: Henry    時間: 2011-11-26 19:56

引用:
原帖由 qcmadness 於 2011-11-26 19:33 發表

Android同Windows唔同, 係要做野.
Windows都係.......
唔係就Load雙核開四核.....
作者: qcmadness    時間: 2011-11-26 19:57

引用:
原帖由 Henry 於 2011-11-26 19:56 發表

Windows都係.......
唔係就Load雙核開四核.....
windows d thread會跳來跳去
作者: Henry    時間: 2011-11-26 20:03

引用:
原帖由 qcmadness 於 2011-11-26 19:57 發表

windows d thread會跳來跳去
所以可能要Windows出Patch Load曬所有Background落一粒槓桿CPU(Random)到,然後空出其他CPU比其他大食Program.
作者: qcmadness    時間: 2011-11-26 20:08

引用:
原帖由 Henry 於 2011-11-26 20:03 發表

所以可能要Windows出Patch Load曬所有Background落一粒槓桿CPU(Random)到,然後空出其他CPU比其他大食Program.
barcelona / K10出過事 (thread scheduling), m$都唔肯攪
作者: cheungmanhoi    時間: 2011-11-26 20:49

引用:
原帖由 Henry 於 2011-11-26 18:10 發表

NV粒Kai-EI已經係(4+1)，不過個效能成本方面的確值得考慮。始終要額外面積，而且係分開運行。
所以nv一定唔夠地頭虫打
ti 一早已經係行a9+m7(無記錯
同埋 arm 都推出左a15+a7啦

[ 本帖最後由 cheungmanhoi 於 2011-11-26 20:51 編輯 ]
作者: Henry    時間: 2011-11-27 01:19

引用:
原帖由 qcmadness 於 2011-11-26 20:08 發表

barcelona / K10出過事 (thread scheduling), m$都唔肯攪
K10/Barcelona......做壞左個頭,M$即刻縮沙.
但始終省得1W得1W係Notebook/Tablet既目標,Desktop某程度都要.
作者: qcmadness    時間: 2011-11-27 01:20

引用:
原帖由 Henry 於 2011-11-27 01:19 發表

K10/Barcelona......做壞左個頭,M$即刻縮沙.
但始終省得1W得1W係Notebook/Tablet既目標,Desktop某程度都要.
M$係咁fing d thread usage
intel / amd都要設計到預左cpu係咁on / off / on / off
作者: Henry    時間: 2011-11-27 01:29

引用:
原帖由 qcmadness 於 2011-11-27 01:20 發表

M$係咁fing d thread usage
intel / amd都要設計到預左cpu係咁on / off / on / off
Intel同AMD無M$提出要修Windows背景作業架構?
作者: qcmadness    時間: 2011-11-27 01:29

引用:
原帖由 Henry 於 2011-11-27 01:29 發表

Intel同AMD無M$提出要修Windows背景作業架構?
AMD肯定有講, Intel唔知
作者: Henry    時間: 2011-11-27 01:31

引用:
原帖由 qcmadness 於 2011-11-27 01:29 發表

AMD肯定有講, Intel唔知
係咁開關,開機果下D電流唔講得少.
唔知W8有無作出相應改動?
作者: qcmadness    時間: 2011-11-27 01:32

引用:
原帖由 Henry 於 2011-11-27 01:31 發表

係咁開關,開機果下D電流唔講得少.
唔知W8有無作出相應改動?
好似會做CMT optimization
core parking都有可能
作者: Henry    時間: 2011-11-27 01:34

引用:
原帖由 qcmadness 於 2011-11-27 01:32 發表

好似會做CMT optimization
core parking都有可能
CMT優化係唔好比BD D Thread撞車遮.
但Core Parking係將背景作業安排到一個CPU到?
作者: qcmadness    時間: 2011-11-27 01:35

引用:
原帖由 Henry 於 2011-11-27 01:34 發表

CMT優化係唔好比BD D Thread撞車遮.
但Core Parking係將背景作業安排到一個CPU到?
http://www.xtremesystems.org/for ... ng-on-Windows-Seven
作者: Henry    時間: 2011-11-27 01:44

引用:
原帖由 qcmadness 於 2011-11-27 01:35 發表

http://www.xtremesystems.org/for ... ng-on-Windows-Seven
叫HT某條Thread訓教.....
始終起動一個Core要相當時間,無可能又開又關,所以先會想到要將所有背景放係一個CPU到,其他可以關.
睇來到Win7 M$都係未做好優化,Core Parking泊錯車.....
作者: qcmadness    時間: 2011-11-27 01:46

引用:
原帖由 Henry 於 2011-11-27 01:44 發表

叫HT某條Thread訓教.....
始終起動一個Core要相當時間,無可能又開又關,所以先會想到要將所有背景放係一個CPU到,其他可以關.
睇來到Win7 M$都係未做好優化,Core Parking泊錯車..... ...
連HT有左8-10年都攪成咁

咁1年唔夠的CMT, 3年唔夠的power gating
作者: XT    時間: 2011-11-27 01:53

引用:
原帖由 qcmadness 於 2011-11-27 01:46 發表

連HT有左8-10年都攪成咁

咁1年唔夠的CMT, 3年唔夠的power gating
M$ CPU Scheduler = SUCK
作者: Henry    時間: 2011-11-27 01:54

引用:
原帖由 qcmadness 於 2011-11-27 01:46 發表

連HT有左8-10年都攪成咁

咁1年唔夠的CMT, 3年唔夠的power gating

HT由P4 3.06B開始已經開始有,D人都唔明點解HT原本Intel講到好勁但到Win就立即收皮.
但有D軟件真係開到HT個效能出來.....

但而家10年後,原本應該從特定軟件開始擴展到所有軟件既時候,結果而家到係咁.....
終於有人發現Windows個Core Parking泊錯車.

不過XP年代開始應該都有類似機制,唔係既話有得軟件用曬所有CPU效能應該幾可觀先係.
作者: XT    時間: 2011-11-27 02:02

引用:
原帖由 Henry 於 2011-11-27 01:54 發表


HT由P4 3.06B開始已經開始有,D人都唔明點解HT原本Intel講到好勁但到Win就立即收皮.
但有D軟件真係開到HT個效能出來.....

但而家10年後,原本應該從特定軟 ...
windows 汁過晒堆底層野先啦
一味加野落個面推靚佢, 又唔諗下自己無能力食個介面
作者: Henry    時間: 2011-11-27 02:10

引用:
原帖由 XT 於 2011-11-27 02:02 發表

windows 汁過晒堆底層野先啦
一味加野落個面推靚佢, 又唔諗下自己無能力食個介面
唔知Linux個架構有無跟HT或CMT執過,唔係就用邊個OS都係咁.
作者: qcmadness    時間: 2011-11-27 02:11

引用:
原帖由 Henry 於 2011-11-27 02:10 發表

唔知Linux個架構有無跟HT或CMT執過,唔係就用邊個OS都係咁.
有
作者: Henry    時間: 2011-11-27 02:13

引用:
原帖由 qcmadness 於 2011-11-27 02:11 發表

有
但Program使唔使要同OS講要幾多CPU,或等CPU自己分配?

同埋Linux果D背景係分散唔同CPU做定集中一個CPU管理?(雖然我個人覺得同Win一樣)
作者: qcmadness    時間: 2011-11-27 02:17

引用:
原帖由 Henry 於 2011-11-27 02:13 發表

但Program使唔使要同OS講要幾多CPU,或等CPU自己分配?

同埋Linux果D背景係分散唔同CPU做定集中一個CPU管理?(雖然我個人覺得同Win一樣)
auto, BD perform better in linux
作者: XT    時間: 2011-11-27 03:19

引用:
原帖由 Henry 於 2011-11-27 02:13 發表

但Program使唔使要同OS講要幾多CPU,或等CPU自己分配?

同埋Linux果D背景係分散唔同CPU做定集中一個CPU管理?(雖然我個人覺得同Win一樣)
Linux 個 CPU scheduler 識得去分

當然 , program 經 gcc compiler 果陣其實都應該要做手腳
呢層就要睇 linux distribution 識唔識/肯唔肯做
作者: ccw    時間: 2011-11-28 10:34     標題: Ivy Bridge第一批18款型号、规格一览无余



http://news.mydrivers.com/1/210/210479.htm
作者: cheungmanhoi    時間: 2011-11-28 12:31

3470最可取咁WOR
作者: Aware    時間: 2011-11-28 16:32

onx K版冇VT-D :o)
作者: qcmadness    時間: 2011-11-28 19:40

咁保守, 怕死?
作者: Aware    時間: 2011-11-28 19:45

引用:
原帖由 qcmadness 於 2011-11-28 19:40 發表
咁保守, 怕死?
指Intel唔敢出>4GHz？
作者: qcmadness    時間: 2011-11-28 19:48

引用:
原帖由 Aware 於 2011-11-28 19:45 發表

指Intel唔敢出>4GHz？
唔只
作者: Aware    時間: 2011-11-28 21:30

引用:
原帖由 qcmadness 於 2011-11-28 19:48 發表

唔只
即係佢可以再多core/cache落主流U，但係冇咁做？
作者: qcmadness    時間: 2011-11-28 21:32

引用:
原帖由 Aware 於 2011-11-28 21:30 發表

即係佢可以再多core/cache落主流U，但係冇咁做？
唔推頻, 唔加core

即係要成本重視
作者: Henry    時間: 2011-11-29 06:14

引用:
原帖由 ccw 於 2011-11-28 10:34 發表


http://news.mydrivers.com/1/210/210479.htm
S都3.1G ......再遲下可能S同K同頻.
或者K仔由77W直落65W.
作者: Henry    時間: 2011-11-29 06:18

引用:
原帖由 Aware 於 2011-11-28 16:32 發表
onx K版冇VT-D :o)
但3770 Non-K終於用返最上級IGP,唔超既話都唔使為個IGP買K仔,而且又有VT-D.
i5要最上級IGP就一係S一係K.
作者: Henry    時間: 2011-11-29 06:20

引用:
原帖由 qcmadness 於 2011-11-28 21:32 發表

唔推頻, 唔加core

即係要成本重視
可能IB-E要壓落來.
IB打APU,IB-E打BD.
作者: qcmadness    時間: 2011-11-29 06:50

引用:
原帖由 Henry 於 2011-11-29 06:20 發表

可能IB-E要壓落來.
IB打APU,IB-E打BD.
...
IB-E要明年年尾或更遲
作者: qcmadness    時間: 2011-11-29 06:51

引用:
原帖由 Henry 於 2011-11-29 06:18 發表

但3770 Non-K終於用返最上級IGP,唔超既話都唔使為個IGP買K仔,而且又有VT-D.
i5要最上級IGP就一係S一係K.
所謂最上級IGP = GT520?
作者: Henry    時間: 2011-11-29 07:17

引用:
原帖由 qcmadness 於 2011-11-29 06:51 發表

所謂最上級IGP = GT520?
上 => HD4000
中 => HD2500
下 => HD1XXX (Celeron/Pentium)


睇表所有i7都係用HD4000,有無K都一樣,變左一係K一係VT-D,少左個變數.

效能未測未能定斷,不過如果有GT520個位既話,HD6470/GT520M就可以早抖.

[ 本帖最後由 Henry 於 2011-11-29 07:18 編輯 ]
作者: Henry    時間: 2011-11-29 07:19

引用:
原帖由 qcmadness 於 2011-11-29 06:50 發表

...
IB-E要明年年尾或更遲
而家先出SB-E,都預左.



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