標題: [業界消息] Intel’s 50-core champion: In-depth on Xeon Phi [打印本頁]

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作者: qcmadness    時間: 2012-8-1 19:23     標題: Intel’s 50-core champion: In-depth on Xeon Phi

http://www.extremetech.com/extre ... n-depth-on-xeon-phi

引用:

There are a handful of x86/x86-64 instructions, including a few fairly common ones, that KNC won’t support. The vectorization and scalar instructions that KNC/KNF introduced are also unique — KNC doesn’t support traditional SIMDs like MMX, SSE, or AVX… yet. That “yet” is important, because it’s virtually guaranteed that Intel will cross-pollinate its instruction sets at some point in the future. The Transactional Synchronization Extensions (TSX) set to debut in Haswell might be extremely useful for Knights Corner’s successor.

而家無SSE2真係幾

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作者: Puff    時間: 2012-8-1 21:07

KNC 只 support zmm 512-bit registers. mm, xmm, ymm 全部 banq

[ 本帖最後由 Puff 於 2012-8-1 21:09 編輯 ]

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作者: qcmadness    時間: 2012-8-1 21:08

引用:

原帖由 Puff 於 2012-8-1 21:07 發表
KNC 只 support zmm 512-bit registers. mm, xmm, ymm 全部 banq

可以返屋企訓覺

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作者: Puff    時間: 2012-8-1 21:12

引用:

原帖由 qcmadness 於 2012-8-1 21:08 發表

可以返屋企訓覺

run as co-processor. 大概到 iLRB in SkyLake 都係咁既款。
當 generic x86 processor 就真係蚊訓。

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