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標題: [硬件] Haswell core major changes [打印本頁]

作者: Puff 時間: 2012-9-12 23:37 標題: Haswell core major changes

8-port monster
new port 6: ALU, Branch
new port 7: Store Address
new unit in port 0: FMA
new units in port 1: FMA, FP Multiply (it seems no FMAC hardware reusing for FADD and FMUL instructions as AMD did in BD)
packed integer pipelines are extended to 256-bit wide
datapaths to L1D are now widened to 32B.
L1 data caches with no capacity change, transactional memory support

2 moderate vs 1 fat.

[ 本帖最後由 Puff 於 2012-9-12 23:39 編輯 ]

作者: qcmadness 時間: 2012-9-13 01:16

8 port? i don't think intel can keep the die size down...

作者: qcmadness 時間: 2012-9-13 01:19

http://www.anandtech.com/show/62 ... rformance-estimates

On-die VRAM up to 128MB

作者: Puff 時間: 2012-9-13 20:24

引用:

原帖由 qcmadness 於 2012-9-13 01:16 發表
8 port? i don't think intel can keep the die size down...

The die size is relatively small for Lady Ivy - GT2/4C variant measured 170 mm^2, according to Intel.
GT2/4C variants will not grow too much, perhaps somewhere between 200 mm^2 and 220 mm^2. And GT3 will go for ~300 mm^2 I think.

[ 本帖最後由 Puff 於 2012-9-13 20:26 編輯 ]

作者: qcmadness 時間: 2012-9-13 20:53

引用:

原帖由 Puff 於 2012-9-13 20:24 發表

The die size is relatively small for Lady Ivy - GT2/4C variant measured 170 mm^2, according to Intel.
GT2/4C variants will not grow too much, perhaps somewhere between 200 mm^2 and 220 mm^2. And GT3 ...

IVB 4C variant is more than 170mm^2, probably ~190mm^2

作者: qcmadness 時間: 2012-9-13 23:28

http://www.xbitlabs.com/articles ... ll-uarch-idf_4.html

Caching Improvements

作者: dom 時間: 2012-9-15 15:35

AMD RIP

作者: Puff 時間: 2012-9-15 19:24

引用:

原帖由 qcmadness 於 2012-9-13 20:53 發表

IVB 4C variant is more than 170mm^2, probably ~190mm^2

http://www.anandtech.com/show/5876/the-rest-of-the-ivy-bridge-die-sizes

作者: qcmadness 時間: 2012-9-15 20:33

引用:

原帖由 Puff 於 2012-9-15 19:24 發表

 http://www.anandtech.com/show/58 ... vy-bridge-die-sizes

But still 6-issue to 8-issue > 10% die size increase
GPU improvement > 15%+ die size increase

作者: Puff 時間: 2012-9-15 23:13

引用:

原帖由 qcmadness 於 2012-9-15 20:33 發表

But still 6-issue to 8-issue > 10% die size increase
GPU improvement > 15%+ die size increase

I wouldn't say exactly 10% die size increase, but the height of the chip should increase as the cores are larger.
I do my estimation in this way.

[ 本帖最後由 Puff 於 2012-9-15 23:18 編輯 ]

作者: qcmadness 時間: 2012-9-15 23:15

引用:

原帖由 Puff 於 2012-9-15 23:13 發表

I wouldn't say exactly 10% die size increase, but the height of the chip should increase as the cores are larger.
I do my estimation in this way.

the change in gpu will raise core size by more than 15%

作者: Puff 時間: 2012-9-15 23:17

引用:

原帖由 qcmadness 於 2012-9-15 23:15 發表

the change in gpu will raise core size by more than 15%

GT2 is with only 20 EUs. 4 more as compared to Ivy
8*20 to 12*20 is already a big jump for the extra 4 EUs and larger cores.

作者: qcmadness 時間: 2012-9-16 10:37

引用:

原帖由 Puff 於 2012-9-15 23:17 發表

GT2 is with only 20 EUs. 4 more as compared to Ivy
8*20 to 12*20 is already a big jump for the extra 4 EUs and larger cores.

it is a fair estimation that intel will make 4c/40eu and 2c/20eu masks

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