(probably) 6-issue execution engine, e.g. capable of 4 INT adds + 2 FP adds in parallel. He didn't mentioned it is with NEON INT or not. But given VFP, NEON FP and NEON INT are often implemented with the same execution unit, it seems we can assume it is 4 ALUs (two of them share issue port with address generation, or the ALUs themselves do a double duty) + 2 NEON pipelines.
In addition, it can sustain two loads or two stores per clock, aligning to the desktop microarchitectures.
