XT

咁仲要咁多 L2 做咩野!?

qcmadness

引用:

Originally posted by 真．飛鳥 at 2007-3-31 15:36:
咁仲要咁多 L2 做咩野!?

你心水果然清過一d人

我都想知.

XT

引用:

Originally posted by qcmadness at 2007-3-31 15:59:

你心水果然清過一d人

我都想知.

我點可以同 EPC班 聚苯乙烯 相題並論

最好笑係 提升到 6MB / 12MB 咁先恐怖 ...

貪製造成本高!? 而且起 E6300同E6320 都睇到多2MB L2都作用唔係太大

qcmadness

引用:

Originally posted by 真．飛鳥 at 2007-3-31 16:37:
我點可以同 EPC班 聚苯乙烯 相題並論
最好笑係 提升到 6MB / 12MB 咁先恐怖 ...
貪製造成本高!? 而且起 E6300同E6320 都睇到多2MB L2都作用唔係太大

根本係marketing問題多過performance.

XT

引用:

Originally posted by qcmadness at 2007-3-31 16:46:


根本係marketing問題多過performance.

簡直係晒錢
最衰無高時脈小小既 2MB L2 版

qcmadness

引用:

Originally posted by 真．飛鳥 at 2007-3-31 16:51:
簡直係晒錢
最衰無高時脈小小既 2MB L2 版

根本而家玩分級,
AMD都會係咁.

XT

引用:

Originally posted by qcmadness at 2007-4-1 23:53:

根本而家玩分級,
AMD都會係咁.

硬係覺得 Intel 起到設個局 , 等 AMD 玩埋一份之後燒佢錢減低C/P

qcmadness

引用:

Originally posted by 真．飛鳥 at 2007-4-2 11:35:

硬係覺得 Intel 起到設個局 , 等 AMD 玩埋一份之後燒佢錢減低C/P

所以multi-core, AMD玩唔起.

XT

引用:

Originally posted by qcmadness at 2007-4-2 16:11:

所以multi-core, AMD玩唔起.

係喎 ,
K8L 都有 IMC , 咁做乜仲要整 L3

qcmadness

引用:

Originally posted by 真．飛鳥 at 2007-4-2 16:31:

係喎 ,
K8L 都有 IMC , 咁做乜仲要整 L3

Data sharing between cores.
The L3 cache design is also exclusive.