dom

INTEL 45nm 技術 , 原生四核都要 130W TDP
點解呢

dom

其實會唔會打多左 , 到實物出個陣就好涼

dom

http://processorfinder.intel.com/details.aspx?sSpec=SLAWM
其實 應該讚 Intel good job

塞埋個 IMC DDR3 Tri-Channel  , 塞埋 QPI
竟然重跌左 TDP 少少

Tommi_Vercetti

其中一個最大問題在於可超性，做不回兩春時代的好超…

小童

引用:

Originally posted by dom at 2008-9-17 22:01:
INTEL 45nm 技術 , 原生四核都要 130W TDP
點解呢

AMD

trentcys

引用:

Originally posted by dom at 2008-9-17 22:01:
INTEL 45nm 技術 , 原生四核都要 130W TDP
點解呢

由LGA775 platform開始Intel o既TDP係照成個class最高o既TDP黎公佈.
而家Yorkfield o既top model (QX9650 & 9770)都係130W TDP, Nehalem o既公佈數據一d都唔出奇

trentcys

引用:

Originally posted by dom at 2008-9-18 00:40:
http://processorfinder.intel.com/details.aspx?sSpec=SLAWM
其實 應該讚 Intel good job

塞埋個 IMC DDR3 Tri-Channel  , 塞埋 QPI
竟然重跌左 TDP 少少

其實同樣quad core, Yorkfield去到Nehalem o既transistor count反而少左89m. (820m -> 731m)
就算少左2MB cache (Nehalem: 256KB L2 per core + 8MB L3 = 10MB) 都只係計75m transistors.
原本P4 QPB o既interface都知佢用左唔少transistor count, 但唔通仲多過而家QPI + IMC??? (當其他improvements會增加transistor count)

qcmadness

引用:

Originally posted by trentcys at 2008-10-5 18:30:


其實同樣quad core, Yorkfield去到Nehalem o既transistor count反而少左89m. (820m -> 731m)
就算少左2MB cache (Nehalem: 256KB L2 per core + 8MB L3 = 10MB) 都只係計75m transistors.
原本P4 QPB o既 ...

Transistor count好難咁計, 因為唔同的caching system會有唔同
尤其係Core Arch.的caching異常複雜

trentcys

引用:

Originally posted by qcmadness at 2008-10-6 21:41:


Transistor count好難咁計, 因為唔同的caching system會有唔同
尤其係Core Arch.的caching異常複雜

但係interface/sharing logic應該冇大改?
只係由L2變成L3

[ Last edited by trentcys on 2008-10-7 at 00:49 ]

qcmadness

引用:

Originally posted by trentcys at 2008-10-7 00:47:


但係interface/sharing logic應該冇大改?
只係由L2變成L3

[ Last edited by trentcys on 2008-10-7 at 00:49 ]

Shared的方式可能不同