qcmadness

http://www.anandtech.com/show/77 ... 8core-opteron-a1100

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The real question is what architecture(s) AMD plans to use to get to a leadership position among ARM CPUs and a substantial share of the x86 CPU market. We get the first hint with the third bullet above: "smaller more efficient x86 CPUs will be dominant in the x86 segment".

Jaguar will come stronger?

Puff

Ambiguous statement as usual. Not necessarily Cats I would say, but Cat's design methodology (automation driven) + higher per-core performance yet in a smaller size and nice perf/watt. If you look at what x86 are positioned for after ARM is added into the mix, they would be APUs with low core count and scalable MP CPUs.

[ 本帖最後由 Puff 於 2014-1-30 17:26 編輯 ]

qcmadness

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原帖由 Puff 於 2014-1-30 17:23 發表
Ambiguous statement as usual. Not necessarily Cats I would say, but Cat's design methodology (automation driven) + higher per-core performance yet in a smaller size and nice perf/watt. If you look at  ...

Intel is doing the same

Puff

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原帖由 qcmadness 於 2014-1-30 17:25 發表

Intel is doing the same

thus the major diffs are the choice of heterogeneous solution and what are being used to address the bottom scaling over the spectrum. AMD may have a mid-term competitive advantage with ARM, as ARM is currently dominant in the low-power handheld space, but speaking of long run Intel has a lot of capital to burn.

qcmadness

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原帖由 Puff 於 2014-1-30 17:31 發表

thus the major diffs are the choice of heterogeneous solution and what are being used to address the bottom scaling over the spectrum. AMD may have a mid-term competitive advantage with ARM, as ARM i ...

But Intel's manufacturing edge is less now

Puff

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原帖由 qcmadness 於 2014-1-30 17:32 發表

But Intel's manufacturing edge is less now

Whatever as it depends on whether Intel can break into that market with x86, or drastically turn the big ship towards ARM.



But the main idea is that AMD would likely converge their x86 lines, as they no longer need two cores to scale x86 spectacularly*. The converged core, if any, should be positioned like K10+++ or Haswell.


*: In the way they projected in 2006/07. Cats was intended to scale down beyond 1 watt IIRC. But now it is the job of ARM solutions. (late edit)

[ 本帖最後由 Puff 於 2014-1-30 17:49 編輯 ]

qcmadness

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原帖由 Puff 於 2014-1-30 17:36 發表

Whatever as it depends on whether Intel can break into that market with x86, or drastically turn the big ship towards ARM.



But the main idea is that AMD would likely converge their x86 lines ...

No...

It seems AMD will concentrate with ARM (<0.5-5W) and x86 (5W+) for each core

Puff

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原帖由 qcmadness 於 2014-1-30 17:50 發表

No...

It seems AMD will concentrate with ARM (

I don't see contradiction. Basically I meant what you mean here.


Perhaps also with a lower frequency ceiling wrt custom designs like Haswell or BD.

[ 本帖最後由 Puff 於 2014-1-30 17:58 編輯 ]

qcmadness

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原帖由 Puff 於 2014-1-30 17:56 發表

I don't see contradiction. Basically I meant what you mean here.


Perhaps also with a lower frequency ceiling with regard to custom designs like Haswell or BD.

5W/core in x86 space is very low indeed.

Puff

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原帖由 qcmadness 於 2014-1-30 17:58 發表

5W/core in x86 space is very low indeed.

If you mean SOC TDP divided by core count, then yes. 5 watts of absolute power per core in a notebook-class SOC is significant, anyway.

Puff

The argument is that it is useless to build two cores, aiming for a similar power performance and scaling, but with different ISAs. It is clear that AMD targets just dense server, embedded and handheld with ARMv8 based on the current bits of information... So it completely overlaps with Cat's initiatives (recall your memories in 07-10). As currently it is just a licensee of ARM and probably it treats the IP acquisition cost as the cost of early market entrance (so that it can release their first wave of ARMv8 product way before the current two core roadmaps, aka BD/CAT, end & the custom core, if any, is ready), it is not a huge prob at all.

However, when it comes to the stage of building a custom core, it becomes a prob. AMD has limited resources, isn't it? Going three microarchitectures, of which two overlaps with each other, is unlikely to happen. You may argue that they wouldn't build a custom ARM core, though.

[ 本帖最後由 Puff 於 2014-1-30 18:33 編輯 ]

qcmadness

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原帖由 Puff 於 2014-1-30 18:13 發表
The argument is that it is useless to build two cores, aiming for a similar power performance and scaling, but with different ISAs. It is clear that AMD targets just dense server, embedded and handhel ...

AMD may not go with custon ARM designs

Puff

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原帖由 qcmadness 於 2014-1-30 20:06 發表

AMD may not go with custon ARM designs

I got one clear messages from AMDer and three signs from LinkedIn that may point to a custom ARM microarchitecture in the pipeline. Another clear message is Bulldozer's irreversible EOL.



[ 本帖最後由 Puff 於 2014-1-30 21:02 編輯 ]

qcmadness

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原帖由 Puff 於 2014-1-30 20:59 發表

I got one clear messages from AMDer and three signs from LinkedIn that may point to a custom ARM microarchitecture in the pipeline. Another clear message is Bulldozer's irreversible EOL.

What kind of "custom" is taking place? CPU-CPU interconnect can be.

Bulldozer's EOL is known already.

Puff

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原帖由 qcmadness 於 2014-1-30 21:05 發表

What kind of "custom" is taking place? CPU-CPU interconnect can be.

"High-level definition of core microarchitecture". There is another "ambidextrous" interconnect project supporting both x86/ARM SOC/chips. Probably ring based. probably.

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Bulldozer's EOL is known already.

Which means either AMD gives up completely the top-half space of PC and server, AMD has yet another high-performance core to succeed it and leaves Cats in its place, or AMD converges to a single core beyond BD & Cat's five-year lifespan.

[ 本帖最後由 Puff 於 2014-1-30 21:16 編輯 ]