qcmadness

http://www.anandtech.com/show/10578/amd-zen-microarchitecture-dual-schedulers-micro-op-cache-memory-hierarchy-revealed

http://www.tomshardware.com/news/amd-zen-microarchitecture-summit-ridge,32508.html

引用:

The early Zen silicon is only clocked at 3 GHz, so AMD downclocked the 6900K (3.2 GHz base and 3.7 GHz turbo) to 3 GHz to normalize the test. We aren't privy to the final Summit Ridge clock speeds, but the company indicated that some SKUs would ship with higher clock speeds when it comes to market. We advise readers to take the test with a grain of salt. AMD did not share test bed details, such as the amount of system RAM, but indicated that the systems had comparable configurations.

The test consisted of a CPU-intensive multi-threaded Blender 3D rendering that scaled across all of the cores. The Summit Ridge CPU rendered the image ever so slightly faster than the Intel 6900K. The contest was close enough that, without a stopwatch, we couldn't give an accurate measurement of the speed difference, and AMD did not provide specific measurements for the test.

dom

*yawn*

qcmadness

Intel server CPU應該會有動作

Aware

引用:

原帖由 qcmadness 於 2016-8-19 19:43 發表
Intel server CPU應該會有動作

最多未再多啲春，有乜動作

XT

引用:

原帖由 qcmadness 於 2016-8-19 19:43 發表
Intel server CPU應該會有動作

膠水又如何

leyland1989

AMD stock price is approaching $8

qcmadness

http://www.anandtech.com/show/10 ... onlevel-parallelism

dom

AMD Zen is very interesting ....

XT

引用:

原帖由 qcmadness 於 2016-8-24 21:53 發表
http://www.anandtech.com/show/10 ... onlevel-parallelism

L0 ITLB ???

qcmadness

引用:

原帖由 XT 於 2016-8-24 23:09 發表

L0 ITLB ???

Trace cache

qcmadness

http://www.anandtech.com/bench/product/1684?vs=1783

Excavator vs Skylate at same clock (turbo)

tat0801

引用:

原帖由 qcmadness 於 2016-8-24 23:29 發表
http://www.anandtech.com/bench/product/1684?vs=1783

Excavator vs Skylate at same clock (turbo)

計CP
終於拉返近
但個製程差異令個功耗都差幾多下

qcmadness

http://dresdenboy.blogspot.hk/20 ... -pre-hot-chips.html

http://dresdenboy.blogspot.hk/20 ... amds-hot-chips.html

Puff

引用:

原帖由 qcmadness 於 2016-8-24 23:12 發表

Trace cache

Not TLB for trace cache. Just small & fast TLB. Predicted IP goes into TLB and then heads to both op cache & ICache. You have L0 DTLB too.


[ 本帖最後由 Puff 於 2016-9-3 17:42 編輯 ]

qcmadness

http://www.xtremesystems.org/for ... ating-perf-at-300-!