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[硬件] 原來K10個L1 cache無問題

原來K10個L1 cache無問題

http://www.digit-life.com/articles3/cpu/rmma-phenom.html

但係SSEx的問題變左仲難解釋

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難道是對AMD SSE優化不足?

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引用:
Originally posted by Tommi_Vercetti at 2008-3-3 23:01:
難道是對AMD SSE優化不足?
咁既話, 改過個complier就攪掂,
但而家唔似...

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引用:
Originally posted by qcmadness at 2008-3-3 23:02:

咁既話, 改過個complier就攪掂,
但而家唔似...
但在link中的test report都ok bor.....

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引用:
Originally posted by Tommi_Vercetti at 2008-3-3 23:06:
但在link中的test report都ok bor.....
所以更加難解釋...

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引用:
Originally posted by qcmadness at 2008-3-3 23:07:


所以更加難解釋...
AMD 將D好簡單既野搞到好煩 , 結果令到成個結構好煩好煩

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引用:
Originally posted by 真.飛鳥 at 2008-3-3 23:10:

AMD 將D好簡單既野搞到好煩 , 結果令到成個結構好煩好煩
Intel係仲恐怖

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引用:
Originally posted by qcmadness at 2008-3-3 23:11:


Intel係仲恐怖
Intel 起碼清楚佢做緊咩野先

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引用:
Originally posted by 真.飛鳥 at 2008-3-3 23:13:

Intel 起碼清楚佢做緊咩野先
但設計遠遠麻煩好多

Shared L2 cache, Micro-ops fusion
呢d你估易架

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引用:
Originally posted by qcmadness at 2008-3-3 23:13:

但設計遠遠麻煩好多

Shared L2 cache, Micro-ops fusion
呢d你估易架
咁反而要問AMD啦

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引用:
Originally posted by 真.飛鳥 at 2008-3-3 23:15:
咁反而要問AMD啦
IMC都難整架

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