Puff

引用:

原帖由 qcmadness 於 2013-8-28 17:54 發表

why use 6t as a few watts are not a concern?

to me, insisting on 6t is a little bit dumb

yield. and perhaps you've to look for where the 1.4 billion (you said 1T, so let it be 1.7-1.7/6) transistors are spent if you do keep your mind, or are you gonna think northbridge + audio DSP + memory controller can spend over 2 billion transistors - even more than the Trinity APU?

[ 本帖最後由 Puff 於 2013-8-28 17:59 編輯 ]

qcmadness

引用:

原帖由 Puff 於 2013-8-28 17:56 發表

yield. and perhaps you've to look for where the 1.4 billion transistors are spent if you do keep your mind, or are you gonna think northbridge + audio DSP + memory controller can spend more than 2 bi ...

yield?

only recent cpu use 6t sram as power concerns, older ones use 4t sram.

yield on 4t sram will be higher

and 6t sram with 32mb costs 1.5b+ transistors, don't get why you insist on that

and 1.5b is bare SRAM without controlling and redundancy

Puff

引用:

原帖由 qcmadness 於 2013-8-28 18:00 發表

yield?

only recent use 6t sram, older ones use 4t sram.

yield on 4t sram will be higher

and 6t sram with 32mb costs 1.5b+ transistors, don't get why you insist on that

well, i have written all the reasons (and also estimation) behind my stand in the previous post. you just have them ignored. 6T-SRAM could be wrong, but 1T-SRAM is never the choice (to me) judging from all the available information.

P.S. the SRAM isn't a cache but a plain scratchpad, so overhead of control logic is minimized.



[ 本帖最後由 Puff 於 2013-8-28 18:06 編輯 ]

qcmadness

引用:

原帖由 Puff 於 2013-8-28 18:05 發表

well, i have written all the reasons (and also estimation) behind my stand in the previous post. you just have them ignored. 6T-SRAM could be wrong, but 1T-SRAM is never the choice (to me) judging fr ...

because you think from customer only

Puff

引用:

原帖由 qcmadness 於 2013-8-28 18:06 發表

because you think from customer only

let's wait and see. look forward to seeing chipwork's die shot.

qcmadness

引用:

原帖由 Puff 於 2013-8-28 18:05 發表

well, i have written all the reasons (and also estimation) behind my stand in the previous post. you just have them ignored. 6T-SRAM could be wrong, but 1T-SRAM is never the choice (to me) judging fr ...

I don't mention 1t at all

what I get is from Xbox 360 data, which is much more logical then your wild estimation based on jaguar

Puff

引用:

原帖由 qcmadness 於 2013-8-28 18:08 發表

what I get is from Xbox 360 data, which is much more logical then your wild estimation based on jaguar

And yours aren't logical at all, as you assume it uses eDRAM but it doesn't seem right. Note that they reiterate eSRAM for many times. Also the die area estimation somehow doesn't fit your super-small figure (~30 mm^2?), or either you expect a high rate of IP block-level redundancy (say 30-50%).

Well, perhaps I could be wrong in the type of SRAM used, but at least my estimation in die area matches my estimiation in transistor budget.

Late Edit:

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I don't mention 1t at all

Sorry for misquote. It should be eDRAM then, 1 capacitor per bit and smaller than 1T-SRAM.


Late Edit 2:
AnandTech seems to agree that XB1 uses 6T-SRAM. So I'm not alone.

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To make up for the gap, Microsoft added embedded SRAM on die (not eDRAM, less area efficient but lower latency and doesn't need refreshing). All information points to 32MB of 6T-SRAM, or roughly 1.6 billion transistors for this memory.

[ 本帖最後由 Puff 於 2013-8-28 18:26 編輯 ]

qcmadness

引用:

原帖由 Puff 於 2013-8-28 18:12 發表

And yours aren't logical at all, as you assume it uses eDRAM but it doesn't seem right. Note that they reiterate eSRAM for many times. Also the die area estimation somehow doesn't fit your super-smal ...

Too high cost for this application

Puff

http://semiaccurate.com/2013/09/ ... ch-more-than-audio/

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All the caches on the die total up to about 47MB so that will dominate the SoC’s area, about half the die according to the architect, much of which is distributed to the various units.