qcmadness

Cache and latency?

qcmadness

引用:

原帖由 Puff 於 2015-10-3 18:04 發表

4-cycle L1 load-use. SSE/AVX seems take no extra cycle. no evidence on L2 latency.

L2 and L3 cache latencies are crucial.

qcmadness

引用:

原帖由 Puff 於 2015-10-5 09:38 發表
Per the patch, Zen core can issue only one 128-bit FMAC per clock only, since FMAC was modelled as `(fp0+fp3)|(fp1+fp3)`. It could be a typo though, since the latency of 256-bit FMAC is not modelled a ...

256-bit FMAC is not so relevant.

INT performance, cache penalties are more relevant.

qcmadness

就咁睇唔太夠AGU