qcmadness

引用:

Originally posted by 真．飛鳥 at 2008-3-11 19:38:


我無野講 , 16MB L3 Share Cache , 人地AMD搞咁耐都仲係得個吉 , 家陣Intel搞掂

呢d唔會賣得平

隨時同Itanium一樣天價

qcmadness

引用:

Originally posted by 真．飛鳥 at 2008-3-11 20:20:

暫時定位係Xeon路線
但無形係給AMD好大壓力 , 你睇下K10

咁既transistor count, 又係照鏡die

p.s. 16MB L3 cache => 16x8x6x1048576=805M => ~200mm^2 (45nm)

qcmadness

引用:

Originally posted by 真．飛鳥 at 2008-3-11 20:26:

Share L3 Cache 喎

單係L3 cache就200mm^2
Core Arch的core w/o cache都要25mm^2 per core啦

仲有cross-bar / FSB interface呢

加加埋埋夠照鏡