qcmadness

引用:

Originally posted by trentcys at 2008-10-5 18:30:


其實同樣quad core, Yorkfield去到Nehalem o既transistor count反而少左89m. (820m -> 731m)
就算少左2MB cache (Nehalem: 256KB L2 per core + 8MB L3 = 10MB) 都只係計75m transistors.
原本P4 QPB o既 ...

Transistor count好難咁計, 因為唔同的caching system會有唔同
尤其係Core Arch.的caching異常複雜

qcmadness

引用:

Originally posted by trentcys at 2008-10-7 00:47:


但係interface/sharing logic應該冇大改?
只係由L2變成L3

[ Last edited by trentcys on 2008-10-7 at 00:49 ]

Shared的方式可能不同