其實而家單轉製程本身已經無乜得益
因為而家leakage又大, variation又高
e.g. 22nm
http://www.realworldtech.com/page.cfm?ArticleID=RWT031411013528引用:
The single biggest cause of variation is random dopant fluctuation (RDF), where the dopant atoms that are implanted in the transistor channel are unevenly distributed. Once this was not an issue, however the size of transistors and the number of dopant atoms small enough that the density can fluctuate significantly.
Other contributors to variation are systematic, rather than random, and determined by the context of a transistor. Transistors can impact the performance of their neighbors, so a single transistor cannot be considered in isolation and depends on the context. For instance, strained silicon improves transistor performance, the strain is impacted by nearby layout structures.
以前Intel / AMD果d咩strained silicon呀, high-K metal gate呀,
low-K electric呀, restrictive design rules (例如gate-last)呀之類
22nm / 20nm全部都要用
講番Intel, 用FinFET會降低yield絕對唔出奇
不過佢仲有4個月搞, 有必要會respin,
如果1月都搞唔掂既話, 可能會縮小規模掛 (e.g. 先推4-core version)
