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http://www.tomshardware.com/news ... e-Layout,14782.html

引用:

As discussed at the IEEE International Solid-State Circuits Conference, Intel engineer Scott Siers announced that there will be four different Ivy Bridge die models. In addition, Ivy Bridge will carry up to 1.4 billion transistors that span over an area of 160 mm2, which is about 26 percent smaller than the comparable 216 mm2 Sandy Bridge die with 1.16 billion transistors. Ivy Bridge is built on 22 nm process, which is the "tick" process of Intel's Tick Tock Model.

引用:

As Scott Siers announced, there will be four different variants of the Ivy Bridge die models.

• 4+2: All four cores enabled, full 8 MB L3 cache enabled, all 16 shader cores (EUs) of the IGP enabled
  
• 2+2: Two cores enabled, 4 MB L3 cache enabled, all 16 shader cores of the IGP enabled
  
• 4+1: All four cores enabled, 6 MB L3 cache enabled, fewer shader cores of the IGP enabled
  
• 2+1: Two cores enabled, 3 MB L3 cache enabled, fewer shader cores of the IGP enabled
  

qcmadness

引用:

原帖由 jackli 於 2012-2-27 23:57 發表
仲系HD3000, 人地AMD APU 打到黎喇

細細聲: 其實HD6410 (A4-3300) 都快過HD3000