qcmadness

http://www.anandtech.com/show/77 ... 8core-opteron-a1100

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The real question is what architecture(s) AMD plans to use to get to a leadership position among ARM CPUs and a substantial share of the x86 CPU market. We get the first hint with the third bullet above: "smaller more efficient x86 CPUs will be dominant in the x86 segment".

Jaguar will come stronger?

qcmadness

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原帖由 Puff 於 2014-1-30 17:23 發表
Ambiguous statement as usual. Not necessarily Cats I would say, but Cat's design methodology (automation driven) + higher per-core performance yet in a smaller size and nice perf/watt. If you look at  ...

Intel is doing the same

qcmadness

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原帖由 Puff 於 2014-1-30 17:31 發表

thus the major diffs are the choice of heterogeneous solution and what are being used to address the bottom scaling over the spectrum. AMD may have a mid-term competitive advantage with ARM, as ARM i ...

But Intel's manufacturing edge is less now

qcmadness

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原帖由 Puff 於 2014-1-30 17:36 發表

Whatever as it depends on whether Intel can break into that market with x86, or drastically turn the big ship towards ARM.



But the main idea is that AMD would likely converge their x86 lines ...

No...

It seems AMD will concentrate with ARM (<0.5-5W) and x86 (5W+) for each core

qcmadness

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原帖由 Puff 於 2014-1-30 17:56 發表

I don't see contradiction. Basically I meant what you mean here.


Perhaps also with a lower frequency ceiling with regard to custom designs like Haswell or BD.

5W/core in x86 space is very low indeed.

qcmadness

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原帖由 Puff 於 2014-1-30 18:13 發表
The argument is that it is useless to build two cores, aiming for a similar power performance and scaling, but with different ISAs. It is clear that AMD targets just dense server, embedded and handhel ...

AMD may not go with custon ARM designs

qcmadness

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原帖由 Puff 於 2014-1-30 20:59 發表

I got one clear messages from AMDer and three signs from LinkedIn that may point to a custom ARM microarchitecture in the pipeline. Another clear message is Bulldozer's irreversible EOL.

What kind of "custom" is taking place? CPU-CPU interconnect can be.

Bulldozer's EOL is known already.

qcmadness

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原帖由 Puff 於 2014-1-30 21:10 發表

"High-level definition of core microarchitecture". There is another "ambidextrous" interconnect project supporting both x86/ARM SOC/chips. Probably ring based. probably.



Which means either ...

Beefing up Jaguar is an option.

It is already on par with K8 / Pilediver IPC wise.

qcmadness

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原帖由 Puff 於 2014-1-30 21:18 發表

Literally means the same as convergence of two cores.

Anyhow, AMD already demonstrated their commitment to drive high-performance core towards Cat's automated design methodology in HC24.

Not convergence

Improve from Jaguar using K10.5 and Bulldozer experiences

qcmadness

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原帖由 Puff 於 2014-1-30 21:23 發表

You know what I mean. A far-stronger Jaguar capable of 3-3.5GHz clock would be nice. Give it more execution resources and larger windows, stick it with a ring interconnect and overhauled cache hierar ...

For example:

1. 3 AGUs with L/S capability
2. One more ALU
3. 6-8 3GHz+ cores


Jaguar:


AMD Hammer (K8):

qcmadness

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原帖由 Puff 於 2014-1-30 21:40 發表
Strong L/S system is preferred over more ALUs.
Say Load Queue with 64+ entries and Store Queue with 32+ entries.
Super fast L2 would be great, particularly  

Too big for each core

qcmadness

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原帖由 Puff 於 2014-1-30 21:43 發表

I guess it would be fine for automated designs... ALU won't occupy too much space, but the L/S unit will. Server workloads rely on the perf of the later tho.


P.S. Broadcom Vulcan Core

x86 is far more transistor-hungry than ARM

qcmadness

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原帖由 Puff 於 2014-1-30 21:50 發表

well I doubt it would be really a lot when you look at Intel's implementation. It just burns more transistors on decoding/microcode and a sophisticated load-store unit due to x86's strict memory orde ...

Remember Intel has the highest-density cache in the industry.
And Intel has control over the fabrication / manufacturing.

qcmadness

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原帖由 Puff 於 2014-1-30 23:11 發表

no matter how it goes, overprovision is always needed for diminishing IPC improvements. The 3.1mm2 Jaguar has a plenty of room to grow IMO, particularly when we are talking about perhaps FinFET based ...

Even at 10mm^2, it is still small compared with Steamroller and Haswell

qcmadness

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原帖由 Puff 於 2014-1-30 23:44 發表

plenty of options to fill that up
- less dense for higher frequency (single turbo up to 3+ Ghz would be nice)
- 3 ALU + 3 AGU as you suggested
- Pipelined Multiplier really helps... also better divis ...

SMT is not that useful in client processors.
And I would expect AMD will re-focus in client processors rather than server processsors.