qcmadness

引用:

原帖由 Puff 於 2012-4-15 20:29 發表

我唔覺得關 scheduler 事。
Flex FP 或者 CPU 自己既 Vector Unit 唔理你係 Unified Scheduler 定 Decoupled Co-processor Model 都好，都唔可能會被 GPU 取代。

同 bunch of Compute Units 黎取代 Flex FP ...

做到, 只係而家未做, 如果唔係點樣share resource

qcmadness

引用:

原帖由 Puff 於 2012-4-15 20:38 發表
http://developer.amd.com/afds/assets/presentations/2901_final.pdf
P.17

其實都唔洗我 explain.

of course, but you can load it in different core or execution units in a silicon

qcmadness

引用:

原帖由 Puff 於 2012-4-15 21:25 發表

總覺得我地講緊既野南轅北轍。乜叫 scheduler? 乜野既 scheduler? Schedule D 乜既 scheduler?

use x86 instruction and at the same time, utilize GPU as co-processor

qcmadness

引用:

原帖由 Puff 於 2012-4-15 21:32 發表

咁問題就係呢個 "scheduler" 點運作法，係 pipeline 上乜野位置呀嘛。

replace the current FP scheduler and GPU scheduler

qcmadness

引用:

原帖由 Puff 於 2012-4-15 21:33 發表

Okay. Is there any new ISA extension for this?

no

qcmadness

引用:

原帖由 Puff 於 2012-4-15 21:34 發表

How would you define a GPU scheduler?

Command processor

qcmadness

引用:

原帖由 Puff 於 2012-4-15 21:39 發表

... 你真係覺得可以？
Compute Units 本身就係一個 4- to 40-way SMT 既 "Core" 黎架啦喎。

可以, 但係其實VLIW仲好做

qcmadness

引用:

原帖由 Puff 於 2012-4-15 21:42 發表

點做？
每個 Compute Unit 有自已既 Program Counter，可以跑多過一個 kernel program。用呢個龐然大物黎取代 FPU，咁 CPU vector instructions 係 decode 之後要做乜？

一組VLIW-4 shader已經可以取代4個core FPU, 你估邊樣efficient d?

HD6970 / 24 => 113 GFlops / shader (800MHz)
SandyBridge 2600K => 8 FP * 3.4 x 10^9 * 4 cores = 108.8 GFLOPs (3400MHz)

qcmadness

引用:

原帖由 Puff 於 2012-4-15 21:45 發表

...... 我真係想講兩樣唔同野黎架喎，Efficient 係唔同既地方。

16 VLIW-4 Shaders 夾埋既 SIMD Engine 自己本身已經係一個 Fetch, Decode & Execute 既 Core.
CPU 既 FPU... 係 Out-of-order Scheduler + Execution ...

所以要時間tune到2者融合

唔係Intel/AMD一早做到出來啦

qcmadness

引用:

原帖由 Puff 於 2012-4-15 21:51 發表

咁你講晒姐，我會歸類做 idealistic 囉。
再講，點樣將 CPU 既 FPU instructions translate 做 GPU 既 executable? 如果係 vector + GPR instruction mix 又點？

如果係idealistic, AMD就唔會買ATi, finish

都係果句, 要translate唔難, 但係做到hieracy之類仲難, 因為x86既restriction/memory disambiguation多好多

qcmadness

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原帖由 Puff 於 2012-4-15 21:54 發表

AMD 買 ATi 都唔代表要整 D 乜鬼 CPU fused together with GPU and they become SuperPU muhahahahah.
最後既問題就係 what's the point of doing this. GPU 同 CPU 既 design aim 根本就唔同。

我覺得成件事要從  ...

所以要時間lor, 唔係一早2011年就出左hetergeneous computing啦

qcmadness

引用:

原帖由 Puff 於 2012-4-15 21:55 發表

唔關時間既問題事，而係你出發既角度就係 CPU 同 GPU 最終會 Tightly Fuse 埋一齊。
但事實上無人咁講過。

qcmadness

引用:

原帖由 Puff 於 2012-4-15 21:55 發表

唔關時間既問題事，而係你出發既角度就係 CPU 同 GPU 最終會 Tightly Fuse 埋一齊。
但事實上無人咁講過。

Core-level integration 果種喎。

http://www.xbitlabs.com/news/cpu ... ue_in_2015_AMD.html

引用:

Advanced Micro Devices plans to finally launch its hybrid chips – which feature x86 central processing along with graphics processing cores – code-named Fusion in early 2011, however, according to a vice president of AMD, the second iteration of Fusion processors will not only be heterogeneous in terms of different cores within one piece of silicon, but the cores themselves will process both graphics and general-purpose data.

“The first iteration of Fusion will include a CPU and GPU, but by 2015 the model could change. In the second iteration [in] 2015, you are not going to be able to tell the difference. It's all going away," said Leslie Sobon, vice president of marketing at AMD, reports IDG News agency.

qcmadness

引用:

原帖由 Puff 於 2012-4-15 21:55 發表

唔關時間既問題事，而係你出發既角度就係 CPU 同 GPU 最終會 Tightly Fuse 埋一齊。
但事實上無人咁講過。

Core-level integration 果種喎。

qcmadness

引用:

原帖由 Puff 於 2012-4-15 22:04 發表

Marketing.
佢點 Fusion 都係佢既事，我亦都無 object 過 CPU integrate GPU 既 "controller" 既可能性 (或者 ACE kind of thing，as you like)。AMD 都有 Patent 描述過類似既 implementation。我 object 既係 Replace ...

integrate GPU做fusion, 而家都做到啦

唔需要external ISA, 用番x86就用到CPU+GPU先係買ATi的價值

要chipset, SiS都做到啦
只係要graphics expert, VIA都做到啦

點解要咁大既ATi?