1. Q: 14nm SoC? 包埋MC, USB controller, SATA controller, system agent / crossbar呢d縮細製程都縮唔到die size既野, 仲有幾多transistor budget? 塞粒咩GPU落去? 減埋GPU, 唔好講L3, L1 + L2 cache都唔夠位啦, 仲想4核?
A: PHY 縮唔細一件事，HDL XV density 拍得住 GPU。成粒 Carrizo logic/SRAM 多過 padding PHY 幾多有眼睇
Q: 都係果句, 講到明係high-performance core, 就算係Intel, 2C同4C Haswell都講緊差80mm^2 die size, 你再講就顯得你夾硬來
2. Q: Ringbus用唔小transistor的, 如果加埋GPU, 想200mm^2以下都難
A: XV 有幾大又喺有眼睇, SRAM array 要幾多面積有數計, 14nm 雖然喺 20nm BEOL 但都喺 more than one full node shrink 呀
Q: 但係L1 / L2 cache都唔係perfect shrink, 仲未計AMD要追番performance deficit
就算用45nm的K10.5, 2個core都講緊10mm^2+
3. Q:好啦, Zen係mid/high-end architecture, 你拎來同low-performance既Beema比?
A: 高性能架構唔做得細 SOC? 吓？Client APU 唔跟得 L3? Cache hierarchy 唔可以轉？
Q: 無話唔得, 不過Intel自己控制哂製程, 地球上最advance design team, Core M 2 core都講緊100mm^2, 你唔係以為AMD會一下次由輸Intel好多變到勁過Intel好多下話
4. Q: 單係MC+USB+SATA+system agent都講用左50-60mm^2, 扣埋12-16 CU, 仲可以有幾多die size? 仲有, client CPU講咩L3 cache? 用快既crossbar唔好?
A:12-16CU 就唔喺我講嘅嘢喇, 咪幫我加料好嗎？
Q: 而家Kaveri都講緊8CU, 明年high-performance CPU仲係8CU? AMD有無咁蠢呀?
呢個世界可以講願景, 但係只講理想, 唔考慮現實, 就係而家AMD的現狀
