trentcys

引用:

Originally posted by dom at 2007-12-28 18:38:
點解 AMD 唔學 Intel 整大個 L2 算數?

唔知技術方面係點...

但係以exclsuive cache嘅架構, K7/K8嘅L2 latency & bandwidth本身已經比Intel差好多. 如果將L2做到好似Intel 咁大嘅話, cache performance估計會好難睇下.

反而如果做多一層(ie, L3) cache嘅話, CPU嘅overall available cache會大左, 但又唔會影響L1/L2 performance. (雖然L3嘅latency會仲高...)

trentcys

引用:

Originally posted by HEAVEN‧傑 at 2007-12-27 12:00:
仲有L3同個CPU都係唔同步...
我睇死係佢做唔到
佢喪推個L3,但又慢過L1/2多多聲

[ Last edited by HEAVEN‧傑 on 2007-12-27 at 12:01 ]

冇辦法之中嘅辦法

Exclusive cache嘅size/performance好難balance, 而AMD又唔肯大花R&D去改K8架構.

仲有就係唔知關唔關crossbar switch嘅bandwidth事, K8 DC 2個cores之間係完全靠xbar協調, 去到quad core就變左每個core由L3 fetch data, 可能咁樣per core嘅available I/O bandwidth會大返d...

trentcys

引用:

Originally posted by qcmadness at 2008-1-1 15:02:


L2 latency係有得救, 不過Intel做得好d咁解

我係指exclusive cache inherent 嘅 latency比inclusive架構高...