Puff

TL;DR:
1. AMD prioritises the Zen CPU and FinFET-based graphics in 2016.
2. Zen APU in 2017.
3. Zen Gen 1 has 40% higher IPC over Excavator.
4. AM4: unified socket infrastructure for desktop in 2016.
5. K12 slips to 2017.
6. Cat & Bulldozer are gone for good. Just one x86 core.

AMD:
NOTs
1. No IoT endpoints (low-end microcontroller), no low-end tablets/mobile, no smartphones
2. No custom process technology, Not investing commodity IP
3. Less presence in low-end PC

GOALs
1. Focusing on Gaming, "Immersive platforms" (IoT connected devices), Datacenter, Network Infrastructures
2. High-perf cores, 2.5D/3D packaging, Software & APIs
3. Increased X86 investments, "Focused ARM investments"
4. "Simplified roadmap" - differentiated solutions over providing every options





- New Semi-custom design win. Ramp in 2017?
- PC is expected to be a significant part of revenue over the next few years. EESC over 50%.

Zen
- 1st generation: 40% higher IPC over Excavator
- 2016 availability



K12
- availability in 2017

GCN
- 2x performance per watt
- 2016: FinFET
- HBM


Fiji: 2.5D packaging, HBM memory on package
- GPUs are just the start: Opportunities to extend across AMD product portfolio

SOC
- Coherent HyperTransport based NOC interconnect


2015 Products
- Radeon R9/R7 300 Series, M300 Series
- Fiji "later this year"
- Carrizo first shipment in Q1, high volume ramp in Q2

2016 Products
- All New FX CPUs with Zen CPU cores
- New Desktop & Mobile APUs: Seems like a revision of Carrizo.
No explicit words on being Zen based. Seems that the original Summit Ridge and Bristol Ridge rumor is real.
- All on AM4




2016/17 Server Products
- x86 CPU, High Core Count
- ARM CPU, Storage, Networking & Embedded
Low power envelope like Xeon D or Avoton?
- APU
Multi-Teraflop! HBM?


[ 本帖最後由 Puff 於 2015-5-7 05:13 編輯 ]

Puff

引用:

原帖由 XT 於 2015-5-7 09:27 發表

出粒膠水U頂住先佢又唔肯

壓注落 Zen CPU
如果按 FudZilla 嘅傳聞呢，Opteron 會喺 MCM (2.5D?) 兩至四粒 8C Zen，然後 socket level up to 2P
睇個樣應該喺想 2016 ramp. 因為張 roadmap 得佢可以喺 2016.


[ 本帖最後由 Puff 於 2015-5-7 11:52 編輯 ]

Puff

引用:

原帖由 qcmadness 於 2015-5-7 20:24 發表
邊個話APU行先過CPU架

:0)

你唔提我本來都冇諗住出聲
起碼我大方向冇乜甩漏 喺估佢16最終會出乜嘅細節炒咗
架構細節果啲未出街 下年再講

啊邊個呢


[ 本帖最後由 Puff 於 2015-5-8 15:53 編輯 ]

Puff

引用:

原帖由 qcmadness 於 2015-5-7 20:19 發表
IPC +40%, 但clock rate呢

如果真係clock rate維持到Kaveri既話, 就會係SandyBridge的IPC左右

zen @ finfet clock rate 會屎過 xv 就真喺神績


[ 本帖最後由 Puff 於 2015-5-8 16:26 編輯 ]

Puff

引用:

原帖由 qcmadness 於 2015-5-9 03:04 發表

同樣係32nm SOI, Llano同Trinity clock rate已經差好遠

我好懷疑你對呢d的概念係基於咩原則

一個近K10多過近Bulldozer的架構, 你竟然話推頻容易

you see what you believe
實情喺 XV HDL design + bulk 都推到上 >3 GHz, lower range 慳電咗添
finfet 連 higher freq at constant power/lower power at const freq 都做唔到全世界等佢做乜？


你都識提 Llano，PD 可以差天共地，莫講話 zen 喺乜樣都未知
"近 K10"? 當啲料喺真，high-level diagram 似唔等於啲乜，SNB 同 west mere 夠似啦
個餡變晒呢但喺。莫講話 llano 仲有鑊氣呢個因素可以計下


最後我冇話「容易」，我只喺話好難會唔用 HDL 嘅 zen 上得 finfet 好難差過用佢 >3ghz 冇難度嘅老哥 XV
我諗我地個大腦永遠好難同步


[ 本帖最後由 Puff 於 2015-5-11 20:11 編輯 ]

Puff

引用:

原帖由 qcmadness 於 2015-5-11 20:24 發表


你無提既係> 3GHz, XV用電仲多左

喺冇提
lower power in lower range 用 less perf/watt at higher clock 嚟換
喺呢個 pref/watt 萬歲嘅年代幾 so 呀。再講呢個咪 finfet/new node 可以閃亮登場嘅點


老實我講得好清楚，我覺得「屎過XV喺神績」
就只喺咁

引用:

Shorter pipeline推頻難d係常識吧, 呢d咁基本既野你又唔提?

一嚟 bulldozer pipeline 冇話特別長，長到 prescott 咁
二嚟 zen 有幾長都未知
三嚟 14-cycle Jaguar 就嚟推到上 2.5Ghz 啦，雖然喺 turbo

引用:

聽住先 ...

不嬲都喺聽住先
話時話 2.5D Fiji 點睇？


[ 本帖最後由 Puff 於 2015-5-11 20:51 編輯 ]

Puff

之前堆 slide 會唔會夾咗啲堅料呢
dkanter 話佢睇過 FAD pre-briefing



[ 本帖最後由 Puff 於 2015-5-13 15:16 編輯 ]

Puff

引用:

原帖由 qcmadness 於 2015-5-11 20:56 發表


咪off-die

[ 本帖最後由 Puff 於 2015-5-13 15:09 編輯 ]