Puff

http://semiaccurate.com/2012/09/ ... worlds-memory-tech/

完全 Non-differential??
4.8-6.4 Gbps with power consumption inline to DDR3 (DDR3: 1.6-1.8 Gbps per pin, GDDR5: 4.0-6.0 Gbps per pin)
Reusing DDR3 DIMM socket is possible
Clean signaling under high speed


邊個會用？AMD? Sony? Microsoft?
2.5D integration 有排未到，就算代替方案之內裡 stacked 但連接是 serial link 既 HMC 都係有排。



[ 本帖最後由 Puff 於 2012-9-17 19:24 編輯 ]

Puff

引用:

原帖由 qcmadness 於 2012-9-17 19:24 發表
其他無乜可能

<派膠>我決定唔用 SidePort 呢個字，用 Fusion GPU Local Memory 呢個 term.

Puff

引用:

原帖由 qcmadness 於 2012-9-17 19:27 發表

SidePort類就唔駛限定用DDR-3 interface

佢用 DDR3 DIMM slot 做 prototype 姐，無話唔可以 fuse 落版啵。DDR3 都得啦。
而且老老實實 20nm Server Fusion APU 就算 DDR4 就未必啃得落，除非所有 algorithm 除左 argument read/result write 外完全唔掂 system memory. 就算有 super large cache 都係咁話。如果唔係 Intel 洗乜搞乜鬼 crystalwell.

Puff

Wild Guess:
1. Select APUs in Fall 13 (perhaps?) and Fall 14 to have Fusion GPU Local Memory... either on board or on package
2. 1P/2P Server APU platforms in Fall 13 and Fall 14 to have quad-channel DDR4 support, no GPU local memory
3. Finally APUs in Fall 15 to have 2.5D interposer integration with stacked memory

muahahahahaha

P.S. Fall 13: 20nm (AMD 20nm: probably 2014), Fall 15?: 14nm (AMD 14nm: 2016?)
AMD starting to use TSV/interposer in the 2nd generation APU products built on 20nm seems reasonable. Anyway, all the things above are my own bull*hits. No copyright reserved. Be imaginative!!!


[ 本帖最後由 Puff 於 2012-9-17 22:10 編輯 ]

Puff

引用:

原帖由 dom 於 2012-9-18 00:14 發表
Is that possible AMD make APU w/eDRAM as Cache  *(They do that with GPU on Console )
or onboard "Local Memory" pair with 128MB GDDR5
It's cheap anyway

They won't do eDRAM in APU in a few years. After a half-decade? I don't know.


[ 本帖最後由 Puff 於 2012-9-18 21:35 編輯 ]

Puff

引用:

原帖由 siuba 於 2012-9-19 01:24 發表
唔用differential? 有可能嗎？
hmc intel好大機會係ddr4之後用..所以rambus byebye~ 無人support佢出黎都無用..

研發是為了專利，專利是用來告人