Puff

http://semiaccurate.com/2013/08/26/xbox-one-details-in-pictures/

363 mm2. 32MB eSRAM 我估佔 35-45%。
bonaire 160 mm2, Jaguar QC+L2 26.2mm2
PS4 我估唔過 300 (213+52).

xbox 最大問題可能係 PPLL 之類既 algorithm (e.g. TressFx) 比 DDR3 限住 BW，或者比 eSRAM 局住唔用得 (unbounded memory)。
當然唔排除有秘招 (e.g. Intel Pixel Shader Ordering). btw 睇落係支持 HSA, 如果 GPU 係 bonaire 級.
GPU front-end 2 prim/clk, 同 tahiti/pitcairn/bonaire 同水準, 估計 PS4 應該都係。


[ 本帖最後由 Puff 於 2013-8-27 03:39 編輯 ]

Puff

引用:

原帖由 qcmadness 於 2013-8-27 21:32 發表
http://bbs.hk-spot.com/viewthread.php?tid=70471&page=3

大過350mm^2, 都話左架啦

呢條 thread 係 PS4 喎

Puff

引用:

原帖由 qcmadness 於 2013-8-27 22:11 發表


32MB eDRAM ~ 30mm^2 only

Intel 22nm + 128MB eDRAM = 84mm^2
So at 28mm + 32MB eDRAM ~ 30mm^2

SRAM 喎。

Puff

引用:

原帖由 qcmadness 於 2013-8-27 22:06 發表

PS4都將會類似

我無估算過 xb1，唔評論。

Puff

360 uses eDRAM wor. 2MB 6T-SRAM on 28nm should be sized around 12mm^2 (jaguar's L2 data blocks) Lower frequency headroom may further shrink the size for ten to twenty percent, I think.


1T is possible though, but 6T seems the mainstream of speculation.


[ 本帖最後由 Puff 於 2013-8-28 12:16 編輯 ]

Puff

引用:

原帖由 qcmadness 於 2013-8-28 12:21 發表

Xbox 360 10mb edram is about 64mm^2 @ 80nm

where do you get 6mm^2 per mb @ 28nm from?

Just look at Jaguar CU. Note that tags are coupled to the L2I block.


estimation: for 5.0-5.4 billion transistors
~2b for GPU, ~1.7b for 32MB 6T-SRAM (32MB*1024^2*8bit*6/10^9), ~0.6b to ~0.8b for the 8-core CPU
~0.5b to 0.7b for anything left behind (NB/DDR3/Audio DSP/TrustZone?)
it sounds logical. anyhow it is significantly denser than trinity/llano.

[ 本帖最後由 Puff 於 2013-8-28 13:43 編輯 ]

Puff

引用:

原帖由 qcmadness 於 2013-8-28 17:35 發表

L2 is different with eDRAM

don't mix them up

6T-SRAM. I am sure that I'm clear about the wordings in my posts, and you keep insisting that it uses eDRAM while I said it is not.


[ 本帖最後由 Puff 於 2013-8-28 17:54 編輯 ]

Puff

引用:

原帖由 qcmadness 於 2013-8-28 17:54 發表

why use 6t as a few watts are not a concern?

to me, insisting on 6t is a little bit dumb

yield. and perhaps you've to look for where the 1.4 billion (you said 1T, so let it be 1.7-1.7/6) transistors are spent if you do keep your mind, or are you gonna think northbridge + audio DSP + memory controller can spend over 2 billion transistors - even more than the Trinity APU?

[ 本帖最後由 Puff 於 2013-8-28 17:59 編輯 ]

Puff

引用:

原帖由 qcmadness 於 2013-8-28 18:00 發表

yield?

only recent use 6t sram, older ones use 4t sram.

yield on 4t sram will be higher

and 6t sram with 32mb costs 1.5b+ transistors, don't get why you insist on that

well, i have written all the reasons (and also estimation) behind my stand in the previous post. you just have them ignored. 6T-SRAM could be wrong, but 1T-SRAM is never the choice (to me) judging from all the available information.

P.S. the SRAM isn't a cache but a plain scratchpad, so overhead of control logic is minimized.



[ 本帖最後由 Puff 於 2013-8-28 18:06 編輯 ]

Puff

引用:

原帖由 qcmadness 於 2013-8-28 18:06 發表

because you think from customer only

let's wait and see. look forward to seeing chipwork's die shot.

Puff

引用:

原帖由 qcmadness 於 2013-8-28 18:08 發表

what I get is from Xbox 360 data, which is much more logical then your wild estimation based on jaguar

And yours aren't logical at all, as you assume it uses eDRAM but it doesn't seem right. Note that they reiterate eSRAM for many times. Also the die area estimation somehow doesn't fit your super-small figure (~30 mm^2?), or either you expect a high rate of IP block-level redundancy (say 30-50%).

Well, perhaps I could be wrong in the type of SRAM used, but at least my estimation in die area matches my estimiation in transistor budget.

Late Edit:

引用:

I don't mention 1t at all

Sorry for misquote. It should be eDRAM then, 1 capacitor per bit and smaller than 1T-SRAM.


Late Edit 2:
AnandTech seems to agree that XB1 uses 6T-SRAM. So I'm not alone.

引用:

To make up for the gap, Microsoft added embedded SRAM on die (not eDRAM, less area efficient but lower latency and doesn't need refreshing). All information points to 32MB of 6T-SRAM, or roughly 1.6 billion transistors for this memory.

[ 本帖最後由 Puff 於 2013-8-28 18:26 編輯 ]

Puff

http://semiaccurate.com/2013/09/ ... ch-more-than-audio/

引用:

All the caches on the die total up to about 47MB so that will dominate the SoC’s area, about half the die according to the architect, much of which is distributed to the various units.