Puff

引用:

原帖由 qcmadness 於 2013-11-24 16:34 發表

其實用side-port類技術已經得

叫 GirlFriend 或者 TSMC 加速 TSV maturity 咪得
"sideport" 可以用 HBM，個 spec 新鮮出爐

Puff

引用:

原帖由 qcmadness 於 2013-11-24 17:21 發表

其實根本唔駛
以而家的socket size, 唔駛die stacking, 只要MCM就得 (Intel都係用MCM)

MCM 貴，yield 唔方好，雖然話 AMD 黎緊有粒 embedded GPU 係單封裝 + 128-bit 7Gbps GDDR5
HBM SK Hynix 聲稱 14 年尾量產

Puff

引用:

原帖由 qcmadness 於 2013-11-24 17:29 發表

MCM先唔貴

你諗下Intel mainstream Netburst CPU都用MCM就知唔貴
Yield更加會高, 因為係test好chip先封裝

唔知啦。我問開嘅路人甲係咁講。
不過用呢種 solution 無得搞 lidded package，除非個 socket 再做大佢。

Puff

同埋再往上走 package size 都限住你啦，最後又係 wide i/o 嘅市場。
一粒搞掂，起點 128 GB/s

Puff

引用:

原帖由 qcmadness 於 2013-11-24 17:34 發表

MCM成本平d, 不過用唔到lidded package又係搞笑, Pentium-D咩來

大佬講緊一粒 Trinity size + 4 粒 豬DDR5

Puff

引用:

原帖由 qcmadness 於 2013-11-24 17:38 發表

唔會啦, 1粒起2粒止, 成本太高同埋粒APU賣唔到咁貴, 加4粒的flag-ship APU就要賣US$200以上

依家 Richland top-bin 賣到 $122...

無嘅，最終又係睇實際應用。實際上 (目前) IGP 用途得打機好睇，所以最後價錢又係睇 CPU。Desktop 對 SFF 要求又唔太高。只不過作為 fan屎得閒發夢咁解 (IF TSV 成本 << low-end GDDR/TSV dGPU 成本, integration wins)。

而且 AMD stacked die program 一直 run 緊，上輪 HC24 先出黎講過下野，路邊社 (S|A+路人甲) 傳聞話 10 年嘅 plan 係 C.I. high-end & Kaveri 用 stacked die，當然最後滑鐵盧左，TFE11 有件實物睇下咁解。不過 sk hynix 14 年尾量產 HBM，我係覺得佢地有客嘅 roadmap 會用先會趕住賣街...。

話時話 LPDDR3/DDR4 有 x32... 八粒夠和味。


[ 本帖最後由 Puff 於 2013-11-24 18:14 編輯 ]

Puff

引用:

原帖由 qcmadness 於 2013-11-24 18:29 發表

2 dram chip is enough

if the bandwidth difference is small (e.g. 64b @ 6Gbps vs DDR3), you need sophisticated changes to the video memmgr to utilize all bandwidth available in the system (e.g. texture streaming @ GDDR, framebuffer @ sysmem), or otherwise it will be more or less the same (or only when OEM uses single-channel...). capacity is the next limitation.

well, there is still another choice - off-package HMC with 160 GB/s. No TSV, but requires SerDes.

[ 本帖最後由 Puff 於 2013-11-24 19:22 編輯 ]

Puff

引用:

原帖由 Henry 於 2013-11-24 18:53 發表

Side Port要板廠商配合先得,即係逼人買貴板.

he is claiming in-package memory.

[ 本帖最後由 Puff 於 2013-11-24 19:31 編輯 ]

Puff

引用:

原帖由 qcmadness 於 2013-11-25 08:41 發表

AMD has done it with side-port.
Intel is doing the same for Iris Pro.

That's just a very low-end graphics, and I am talking about maximizing the performance instead of capability. Iris Pro one is cache-based according to the current information, and it is different from having two addressable pools. As far as I know the current video memory manager is just optimized for GPU local memory, i.e. system memory is mainly for spilling/paging and will be accessed directly only at worse case. This could be a problem as if the actual utilized BW is close to the main memory BW (similar BW eventually = similar perf = dedicated pool is no use), but if it is 6+ Gbps then it should be fine (48-56 GB/s)



[ 本帖最後由 Puff 於 2013-11-25 13:06 編輯 ]

Puff

引用:

原帖由 qcmadness 於 2013-11-27 20:14 發表

I will wait and see...

I expect AMD to go for side-port again with 1-2 chips.

Let's wait and see.