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[硬件] 原來K10個L1 cache無問題

引用:
Originally posted by qcmadness at 2008-3-3 23:07:


所以更加難解釋...
AMD 將D好簡單既野搞到好煩 , 結果令到成個結構好煩好煩

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引用:
Originally posted by qcmadness at 2008-3-3 23:11:


Intel係仲恐怖
Intel 起碼清楚佢做緊咩野先

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引用:
Originally posted by qcmadness at 2008-3-3 23:13:

但設計遠遠麻煩好多

Shared L2 cache, Micro-ops fusion
呢d你估易架
咁反而要問AMD啦

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