8-port monster
new port 6: ALU, Branch
new port 7: Store Address
new unit in port 0: FMA
new units in port 1: FMA, FP Multiply (it seems no FMAC hardware reusing for FADD and FMUL instructions as AMD did in BD)
packed integer pipelines are extended to 256-bit wide
datapaths to L1D are now widened to 32B.
L1 data caches with no capacity change, transactional memory support
2 moderate vs 1 fat.
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本帖最後由 Puff 於 2012-9-12 23:39 編輯 ]