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[硬件] Ivy Bridge Info Thread(Updated#2 30-11-2011, @#122)

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原帖由 qcmadness 於 2011-9-15 20:09 發表

發佈果陣一路都話係995M transistor (4-core version)
而家有人追問IVB transistor count

一口氣將SB個transistor count推上1140M
咁佢同BD個competitive advantage無左一大半 ...
Maybe the advantage of Tri-Gate should be taken into account; the advancement may cover the loss due to the transistor number boost.

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原帖由 ccw 於 2011-9-15 20:35 發表

Maybe the advantage of Tri-Gate should be taken into account; the advancement may cover the loss due to the transistor number boost.
咁做咩要出假SB transistor count

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引用:
原帖由 qcmadness 於 2011-9-15 20:40 發表

咁做咩要出假SB transistor count
Sorry, looks I misunderstood your words, any more details?

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引用:
原帖由 ccw 於 2011-9-15 20:44 發表

Sorry, looks I misunderstood your words, any more details?
SB transistor count: 995M > 1160M

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引用:
原帖由 qcmadness 於 2011-9-15 20:45 發表

SB transistor count: 995M > 1160M
I see, just spotted this on Anandtech,
wait for Intels ans then.

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引用:
原帖由 ccw 於 2011-9-15 20:47 發表

I see, just spotted this on Anandtech,
wait for Intels ans then.
http://www.anandtech.com/show/4798/ivy-bridge-148b-transistors

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引用:
原帖由 qcmadness 於 2011-9-16 01:36 發表
http://www.anandtech.com/show/48 ... 5m-are-both-correct

愈講愈衰
無理解錯佢係唔係講DESIGN就995 TAPE OUT就1.16B

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引用:
原帖由 cheungmanhoi 於 2011-9-16 11:48 發表

無理解錯佢係唔係講DESIGN就995 TAPE OUT就1.16B
咁應該報1.16B

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http://www.anandtech.com/show/48 ... hitecture-exposed/1
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As I mentioned above, Ivy Bridge finally supports USB 3.0 natively.
4 USB 3.0 ports across all high-end chipsets.
Still 2 SATA-3 and 4 SATA-2 ports.
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Quad-core Ivy Bridge CPUs will support up to 8MB of L3 cache, and the private L1/L2s haven't increased from their sizes in Sandy Bridge (32+32K/256K).

The memory controller also remains relatively unchanged, aside from some additional flexibility. Mobile IVB supports DDR3L in addition to DDR3, enabling 1.35V memory instead of the standard 1.5V DDR3. This is particularly useful in notebooks that have on-board DDR3 on the underside of the notebook; OEMs can use DDR3L and keep your lap a bit cooler.
A little bit disappointment...
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Memory overclocking also gets a bump in Ivy Bridge. The max supported DDR3 frequency in SNB was 2133MHz, Ivy Bridge moves this up to 2800MHz. You can now also increase memory frequency in 200MHz increments.
Good for OCers, but really useful?
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The System Agent operates on a separate voltage plane than the rest of the chip. On Ivy Bridge Intel now offers even lower System Agent voltage options for the lower voltage SKUs, which in turn helps power optimize those SKUs.
Good for mobile...
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The cTDP up mode is obviously for docked notebooks. You can imagine an Ivy Bridge notebook with an optional dock that could enhance the cooling capabilities of the machine. When undocked the notebook's processor would operate at a max TDP of 17W, for example, but toss it in a dock with additional cooling and the TDP would jump up to 33W. It's up to the OEMs to decide how they want to take advantage of this feature. It could be something as simple as a mobile dock with more fans, or something as complex as a modular water cooling solution with a bigger radiator in the dock. I haven't seen any concepts of systems that take advantage of Ivy Bridge's cTDP up support, but that's the theory.

What about cTDP down? Take the same 17W Ivy Bridge CPU from above but now drop the TDP to 13W, which in turn limits clock speed and voltage. Why would you want to do this? From the OEM perspective, Intel's TDP choices may seem arbitrary. Downwards configurable TDP allows OEMs to get a lower power configuration without forcing Intel to create a new SKU. OEMs can do this today through undervolting/underclocking of their own, but the cTDP down spec will at least give OEMs a guarantee of performance/power.
This is normal and is easily implemented in previous generations of Intel and AMD CPUs...
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The Ivy Bridge GPU adds support for OpenCL 1.1, DirectX 11 and OpenGL 3.1. This will finally bring Intel's GPU feature set on par with AMD's. Ivy also adds three display outputs (up from two in Sandy Bridge). Finally, Ivy Bridge improves anisotropic filtering quality. As Intel Fellow Tom Piazza put it, "we now draw circles instead of flower petals" referring to image output from the famous AF tester.
Eyefinity iGPU version?
Better AF algorithm is always welcomed.
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Ivy Bridge will bring about higher clock speeds thanks to its 22nm process, however the gains will likely be minimal at best. Intel hasn't been too keen on pursuing clock speed for quite some time now. Clock for clock performance will go up by a small amount over Sandy Bridge (4 - 6%), combine that with slightly higher clock speeds and we may see CPU performance gains of around 10% at the same price point with Ivy Bridge. The bigger news will be around power consumption and graphics performance.
This is the most worrying part, Intel surely wants to reduce costs rather than higher performance.
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Ivy Bridge will be Intel's flagship 22nm CPU for some time. The chip was originally due out at the end of this year but was likely subject to delays due to issues with the fab process and the chip itself. The move to 22nm is significant leap. Not only are these new transistors aggressively small but the introduction of Intel's tri-gate technology is a major departure from previous designs. Should the fab engineers at Intel do their job well, Ivy Bridge could deliver much better power characteristics than Sandy Bridge. As we've already seen, introducing a 35W quad-core part could enable Apple (and other OEMs) to ship a quad-core IVB in a 13-inch system.
That's what I posted...

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Ivy Bridge确定明年四月发布 赛扬要没了

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引用:
原帖由 ccw 於 2011-11-24 22:45 發表
http://news.mydrivers.com/1/210/210239.htm
mainly due to hdd shortage

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其實無咩分別, 只系玩左tri-gate 3D

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原帖由 jackli 於 2011-11-24 23:50 發表
其實無咩分別, 只系玩左tri-gate 3D
The difference reflected on the boards tbh.

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引用:
原帖由 jackli 於 2011-11-24 23:50 發表
其實無咩分別, 只系玩左tri-gate 3D
this is not a 3-d gate at all

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