qcmadness

引用:

原帖由 Puff 於 2013-11-24 19:19 發表

if the bandwidth difference is small (e.g. 64b @ 6Gbps vs DDR3), you need sophisticated changes to the video memmgr to utilize all bandwidth available in the system (e.g. texture streaming @ GDDR, fr ...

AMD has done it with side-port.
Intel is doing the same for Iris Pro.

Puff

引用:

原帖由 qcmadness 於 2013-11-25 08:41 發表

AMD has done it with side-port.
Intel is doing the same for Iris Pro.

That's just a very low-end graphics, and I am talking about maximizing the performance instead of capability. Iris Pro one is cache-based according to the current information, and it is different from having two addressable pools. As far as I know the current video memory manager is just optimized for GPU local memory, i.e. system memory is mainly for spilling/paging and will be accessed directly only at worse case. This could be a problem as if the actual utilized BW is close to the main memory BW (similar BW eventually = similar perf = dedicated pool is no use), but if it is 6+ Gbps then it should be fine (48-56 GB/s)



[ 本帖最後由 Puff 於 2013-11-25 13:06 編輯 ]

qcmadness

引用:

原帖由 Puff 於 2013-11-25 12:45 發表

That's just a very low-end graphics, and I am talking about maximizing the performance instead of capability. Iris Pro one is cache-based according to the current information, and it is different fro ...

I will wait and see...

I expect AMD to go for side-port again with 1-2 chips.

Puff

引用:

原帖由 qcmadness 於 2013-11-27 20:14 發表

I will wait and see...

I expect AMD to go for side-port again with 1-2 chips.

Let's wait and see.

~Mars~

多舊魚

加到32 lane pcie 好過啦

用k系玩sli／cf 嘅人肯定多過用iGPU 嘅人 n倍

[ 本帖最後由 ~Mars~ 於 2013-11-28 01:36 編輯 ]