qcmadness

可能係45nm product

HEAVEN‧傑

引用:

Originally posted by qcmadness at 2007-12-26 02:26:
可能係45nm product

Intel玩返低頻高能AMD都唔爭氣...
個人覺得佢個真四核真係得啖笑
仲有佢個SSE4a...

我只係對於佢既Unganged Mode有興趣

dom

我等佢出 Tri-Core 版

Tommi_Vercetti

引用:

Originally posted by HEAVEN‧傑 at 2007-12-26 08:56:

Intel玩返低頻高能AMD都唔爭氣...
個人覺得佢個真四核真係得啖笑
仲有佢個SSE4a...

我只係對於佢既Unganged Mode有興趣

unganged mode = 64-bit x2, 早見過了

HEAVEN‧傑

引用:

Originally posted by Tommi_Vercetti at 2007-12-27 01:35:


unganged mode = 64-bit x2, 早見過了

我只知理論,未睇過test

qcmadness

引用:

Originally posted by HEAVEN‧傑 at 2007-12-27 11:36:

我只知理論,未睇過test

好差

HEAVEN‧傑

引用:

Originally posted by qcmadness at 2007-12-27 11:47:


好差

咁我2號機玩返K8算(新年夠錢既話)

HEAVEN‧傑

仲有L3同個CPU都係唔同步...
我睇死係佢做唔到
佢喪推個L3,但又慢過L1/2多多聲

[ Last edited by HEAVEN‧傑 on 2007-12-27 at 12:01 ]

dom

點解 AMD 唔學 Intel 整大個 L2 算數?

HEAVEN‧傑

引用:

Originally posted by dom at 2007-12-28 18:38:
點解 AMD 唔學 Intel 整大個 L2 算數?

應該係製程能力問題
我諗佢當年整個RAM控制器就係想彌補依方面~

dom

http://www.hkepc.com/?id=550
有人吋 AMD 就算出 K10 @ Stepping B3 都係唔夠打 買黎做乜
平就有人買架啦

bebe2803

迫到 intel 將 d 新款 quad core 減價就

trentcys

引用:

Originally posted by dom at 2007-12-28 18:38:
點解 AMD 唔學 Intel 整大個 L2 算數?

唔知技術方面係點...

但係以exclsuive cache嘅架構, K7/K8嘅L2 latency & bandwidth本身已經比Intel差好多. 如果將L2做到好似Intel 咁大嘅話, cache performance估計會好難睇下.

反而如果做多一層(ie, L3) cache嘅話, CPU嘅overall available cache會大左, 但又唔會影響L1/L2 performance. (雖然L3嘅latency會仲高...)

trentcys

引用:

Originally posted by HEAVEN‧傑 at 2007-12-27 12:00:
仲有L3同個CPU都係唔同步...
我睇死係佢做唔到
佢喪推個L3,但又慢過L1/2多多聲

[ Last edited by HEAVEN‧傑 on 2007-12-27 at 12:01 ]

冇辦法之中嘅辦法

Exclusive cache嘅size/performance好難balance, 而AMD又唔肯大花R&D去改K8架構.

仲有就係唔知關唔關crossbar switch嘅bandwidth事, K8 DC 2個cores之間係完全靠xbar協調, 去到quad core就變左每個core由L3 fetch data, 可能咁樣per core嘅available I/O bandwidth會大返d...

dom

引用:

Originally posted by trentcys at 2007-12-30 15:38:


唔知技術方面係點...

但係以exclsuive cache嘅架構, K7/K8嘅L2 latency & bandwidth本身已經比Intel差好多. 如果將L2做到好似Intel 咁大嘅話, cache performance估計會好難睇下.

...

唉.....唯有等 AMD 改良一下 K10 (K10.5 ? )