qcmadness

http://www.anandtech.com/show/50 ... lving-even-deeper/1

唔易明, 高手攻略

branch prediction原來無事
係penalty太大

Puff

引用:

No matter how rough the current implementation of Bulldozer is, if you look a bit deeper, this is not the architecture that is made for high-IPC, branch intensive, lightly-threaded applications.

If... if Bulldozer and his followings are indeed modular, perhaps AMD will deliver two variants of cores? One for APU with smaller, more responsive caches (perhaps a 8-way 256KB cache..., and please get all second integer cores parked), and one for server with bulk caches. For the IPC issue, Steamroller? seems to have extended the capabilities of AGLUs to execute GPR instructions. One example is register-to-register moves. Let's see if this will help.


Anyway, Bulldozer module with 1MB L2 cache reduces the L2 load-use latency by 1 cycle only. This information is from... errrmm... IEEE 2011 Bulldozer paper.

[ 本帖最後由 Puff 於 2012-5-30 21:17 編輯 ]

XT

引用:

原帖由 qcmadness 於 2012-5-30 19:37 發表
http://www.anandtech.com/show/50 ... lving-even-deeper/1

唔易明, 高手攻略

branch prediction原來無事
係penalty太大

大到變NetBurst

Puff

引用:

原帖由 XT 於 2012-5-30 20:52 發表

大到變NetBurst

無。佢話係大過 Stars，但少過 NetBurst，而且最壞既情況比起 Netburst 都只係九牛一毛 (3x-4x vs 100+)。

dom

引用:

原帖由 qcmadness 於 2012/5/30 19:37 發表
http://www.anandtech.com/show/50 ... lving-even-deeper/1

唔易明, 高手攻略

branch prediction原來無事
係penalty太大

XS 個陣都有討論過
話 L1 出事
有人試停 左 Module 入面其中一組 (?)
話d 性能會 "正常d"

qcmadness

引用:

原帖由 Puff 於 2012-5-30 20:51 發表


If... if Bulldozer and his followings are indeed modular, perhaps AMD will deliver two variants of cores? One for APU with smaller, more responsive caches (perhaps a 8-way 256KB cache..., and please ...

you can save 20% of die size with 1MB shared L2 cache