qcmadness

http://www.electroiq.com/article ... grating-high-k.html

睇後面果一半就得了

引用:

Possible integration schemes for HK/MG

In the early days of the quest for a HK/MG CMOS solution, a rather disruptive approach based on the complete silicidation of the poly-silicon gate electrode, called FUSI, was proposed [3]. This approach, very promising at first due to its integration simplicity, was abandoned later on due to the difficulty in controlling the silicide phase to achieve low VT devices.

Today, two main integration options remain: gate-first (often referred to as MIPS, metal inserted poly-silicon) and gate-last (also called RMG, replacement metal gate). The terminology 'first' and 'last' refers to whether the metal electrode is deposited before or after the high temperature activation anneal(s) of the flow.

The gate-first approach was initially developed by Sematech and the IBM-led Fishkill Alliance. It relies on very thin capping layers — Al2O3 for the PMOS and LaOx for the NMOS transistors — to create dipoles that set the threshold voltage of the device. However, thermal instabilities in HK/MG devices were reported and can lead to threshold voltage shifts and re-growth in the gate stack. This issue is particularly acute for pMOS at scaled EOT, as illustrated in Fig. 3 [4]. At those aggressive EOT, it is clear that RMG can deliver significantly higher EWF (meaning lower pMOS VT) than MIPS. Note that this specific issue impedes essentially the use of gate-first for high performance applications. For low power (LSTP) or DRAM applications, where VT and EOT requirements are typically more relaxed, gate-first remains a very viable and promising option for integrating a cost effective HK/MG CMOS solution [5,6].

Nevertheless, significant efforts to enable gate-first for high-performance applications are still under way. One promising work-around to the high VT issue proposed consists in forming by epitaxy a SiGe channel for pMOS devices [7]. This approach intrinsically lowers VT (through valence band off-set) and presents the additional benefit of higher hole mobility than in Si. However, the extra cost associated with this epitaxy tends to offset the process complexity advantage of gate-first over gate-last.

The second way of integrating HK/MG, with a so-called gate-last process, was initially developed by Intel, implementing it in its 45nm technology [1]. In that iteration, the hafnium dielectric was deposited early on in the flow, prior to a sacrificial polysilicon gate was created. After the high-temperature S-D and silicide annealing cycles, the dummy gate was removed and metal gate electrodes were deposited last. More recently, Intel introduced in their 32nm technology a slightly different scheme where the high-k is deposited last, right before the metal gate electrodes, and after the complete removal of the dummy gates. One possible advantage with this new approach is to improve the device reliability and mobility at scaled EOT, which can be significantly degraded when the high-k dielectric has gone through the high thermal steps of the flow, just like in the gate-first approach case [8].

Recently, UMC disclosed a hybrid approach to integrate HK/MG, combining both gate-first (for nMOS) and gate-last (for pMOS) [9]. This allows the tackling of one of the main challenges of gate-first when targeting high-performance applications, which is the high pMOS VT at scaled EOT, while avoiding the full, complex CMOS gate-last integration that requires multiple CMP steps and dual metal gate deposition. Similar to Intel's 45nm process, this approach is based on a high-k first scheme though, so unless significant progress is being made to improve the thermal stability of the high-k layers, the scalability of this approach to sub-32nm nodes might be difficult. At those advanced nodes, reliability and mobility typically degrade quickly at the target EOT.

One of the concerns often brought up concerning gate-last is its process complexity. As described by Intel [10], the dual metal gates formation involved some critical CMP steps. To maintain sufficient process window, such approach requires more restricted design rules (RDRs), like the 1-D design approach (where gates are all aligned in a given direction). However, at the 28nm node, and more so at the 22nm node, this layout restriction is becoming mainstream anyway, due to lithography constraints. Therefore, the higher design flexibility of gate-first might fade away for the future nodes, as more and more RDRs will need to be implemented.

Looking beyond the 22nm node, the device architecture itself might change from conventional planar to multi-gate (like FinFET or Trigate), in order to improve further the electrostatic control of the device. Those 3D devices might have a significant impact on the integration strategy of HK/MG. Most certainly a CMP-based approach (as in today's RMG flow) would become extremely complex, if not impossible, making the gate-first scheme the only solution.

Ref:
Intel: Gate last from 45nm
TSMC: Gate last from 28nm
UMC: hybrid approach?
Globalfoundries / IBM: 22nm / 20nm