qcmadness

引用:

原帖由 dom 於 2017-1-13 10:52 發表
https://www.techpowerup.com/2295 ... s-with-smt-disabled

New die先係新聞

qcmadness

http://www.linleygroup.com/mpr/article.php?id=11666

qcmadness

引用:

原帖由 Puff 於 2017-2-10 23:41 發表
Retail Price?
http://www.shopblt.com/search/or ... 4&search=Search

source: link from S|A forum

Get the real price at launch

qcmadness

https://www.techpowerup.com/2305 ... ated-to-xfr-feature

qcmadness

引用:

原帖由 dom 於 2017-2-12 04:22 發表
https://twitter.com/Dresdenboy/status/830446602720526336
For QC

1個CCX係66mm^2
即係Summit Ridge係~240-260mm^2

qcmadness

http://www.xtremesystems.org/for ... es-%28per-Reddit%29

qcmadness

http://www.xtremesystems.org/for ... requencies-Revealed

qcmadness

https://www.google.com.hk/url?sa ... st=1487585433374628

Est. die size ~ 200mm^2

qcmadness

引用:

原帖由 Puff 於 2017-2-20 13:22 發表

More interested in how Zeppelin manages to be form a 4-chip MCM. They have a giant PCIe/SerDes PHY block, but I can't say for sure how many 16-lane links there would be. Link speed is unknown too (8  ...

I don't buy the suggestion of 4-chip MCM

qcmadness

http://www.anandtech.com/show/11 ... y-on-sale-march-2nd
http://techreport.com/news/31471 ... ad-the-ryzen-charge
http://www.tomshardware.com/news ... 0x-1800x,33702.html

qcmadness

http://www.xtremesystems.org/for ... upport-NVIDIA-s-SLI

qcmadness

http://www.tweaktown.com/news/56 ... ps-begin/index.html

引用:

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qcmadness

https://www.techpowerup.com/2312 ... mises?cp=2#comments

qcmadness

http://www.tweaktown.com/article ... -preview/index.html

qcmadness

引用:

原帖由 Puff 於 2017-3-11 02:10 發表

It is not really a "design flaw" but apparently an intentional design choice (no system LLC). Yes, it is a bottleneck, but only for implementations that assume a giant shared LLC for all cores, and p ...

The OS needs to be NUMA-aware to fully support Ryzen