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http://www.anandtech.com/show/11 ... anes-epyc-june-20th
http://www.tomshardware.com/news/amd-threadripper-vega-pcie-lanes,34581.html

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引用:

原帖由 XT 於 2017-6-2 20:39 發表
Epyc 個走線 design 同 Ryzen 9 唔同...

source?

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咪又係用Infinic Fabirc / GMI link

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引用:

原帖由 Sandbo 於 2017-6-2 22:56 發表
Judging from the diagram, I wonder if there will be any extra delay going from say top left to bottom right.
Maybe they should implement a cross at the center?

Each Zeppelin has only 2 GMI link.

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引用:

原帖由 tat0801 於 2017-6-7 11:19 發表

成本價
咁大鑊啦，INTEL最唔想做果樣可能都要做

有排都未到成本價

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最新消息: 有1條x16可能係x399拉出來

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引用:

原帖由 BlackBird 於 2017-6-11 17:40 發表

no
但有條x8會係
其實根本就係換個socket然後所有features跟die count黎乘起

但係 Zeppelin 應該跟2條x16

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引用:

原帖由 BlackBird 於 2017-6-13 23:15 發表

我比較好奇跨Die會唔會當numa

2個CCX本來已經有software當numa

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Designed as multi-channel IF links




Welcome RAS features

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http://www.anandtech.com/show/11 ... d-and-epyc-analysis