Totti

http://www.hkepc.com/bbs/viewthr ... &extra=page%3D1

1*48呀笨EPC班友不過ATi又真係16*3

trentcys

Extremely Plastic Community

Richteralan

唔係咩16*3...
呢個rumour要準確D表達pipeline configuration係

16 - 1 - 3 - 1

16 is 16 pipelines
1 is single texture per pass(up to 16 textures for 16 pipes)
3 is 3 fragment(pixel) per pass(up to 48 pixels for 16 pipes)
1 is single Z sample per pass(up to 16 Z samples for 16 pipes)

[ Last edited by Richteralan on 2005-12-27 at 06:52 ]

Richteralan

所以話根本16*3唔可能=48*1

Richteralan

NV47(G70)既pipeline configuration係

24 - 1 - 3/4 - 1 1/4

24 is 24 pipelines
1 is single texture per pass(up to 24 textures for 24 pipes)
3/4 fragment(pixel) per pass(up to 16 pixels for 24 pipes)
1 1/4 Z sample per pass(up to 32 Z samples for 24 pipes)

[ Last edited by Richteralan on 2005-12-27 at 06:49 ]

Richteralan

NV40既pipeline configuration係

16 - 1 - 1 - 2

16 is 16 pipelines
1 is single texture per pass(up to 16 textures for 16 pipes)
1 fragment(pixel) per pass(up to 16 pixels for 16 pipes)
2 Z sample per pass(up to 32 Z samples for 16 pipes)

所以NV47(G70)其實效率減低左DD, 換來既係D附加功能, 例如Gamma corrected AA/Transparent AA等等...

Richteralan

R520既pipeline configuration係

16 - 1 - 1 - 1

trentcys

算啦~
o個邊班細路根本唔識technical野. Cyrix mII係VIA出品都夠膽講

XT

引用:

Originally posted by trentcys at 2005-12-27 12:44:
算啦~
o個邊班細路根本唔識technical野. Cyrix mII係VIA出品都夠膽講

Cyrix係VIA出品!?

trentcys

引用:

Originally posted by 真．飛鳥 at 2005-12-27 13:49:

Cyrix係VIA出品!?

http://www.hkepc.com/bbs/viewthr ... page%3D1&page=2

mIIv個V字係代表2.2V低電壓版本, 條友懶醒V for VIA 經典EPC作風, 識少少扮代表

XT

引用:

Originally posted by trentcys at 2005-12-27 14:36:


http://www.hkepc.com/bbs/viewthr ... page%3D1&page=2

mIIv個V字係代表2.2V低電壓版本, 條友懶醒V for VIA 經典EPC作風, 識少少扮代表

唉 ...

XT